diff mbox series

[RFC,02/13] ARC: Kconfig: introduce option to disable ZOL

Message ID 20220222141506.4003433-3-geomatsi@gmail.com
State New
Headers show
Series ARC: handle the lack of ZOL support | expand

Commit Message

Sergey Matyukevich Feb. 22, 2022, 2:14 p.m. UTC 
From: Vineet Gupta <vgupta@kernel.org>

Upcoming ARCv3 lacks ZOL support, so provide alternatives
based on DBNZ instruction inrtroduced in ARCv2.

Signed-off-by: Vineet Gupta <vgupta@kernel.org>
---
 arch/arc/Kconfig                           | 10 ++++++++
 arch/arc/Makefile                          |  1 +
 arch/arc/include/asm/asm-macro-dbnz-emul.h | 12 +++++++++
 arch/arc/include/asm/asm-macro-dbnz.h      |  8 ++++++
 arch/arc/include/asm/assembler.h           | 29 ++++++++++++++++++++++
 5 files changed, 60 insertions(+)
 create mode 100644 arch/arc/include/asm/asm-macro-dbnz-emul.h
 create mode 100644 arch/arc/include/asm/asm-macro-dbnz.h
 create mode 100644 arch/arc/include/asm/assembler.h
diff mbox series

Patch

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 3c2a4753d09b..9daef7c763ce 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -341,6 +341,16 @@  config ARC_HAS_SWAPE
 
 if ISA_ARCV2
 
+config ARC_LACKS_ZOL
+	bool "Disable Zero Delay hardware loops"
+	help
+	  ARC CPU historically have had ZOL hardware loop mechanism which
+	  the ARCv3 ISA drops. Architecturally ZOL provides
+	    - LPcc instruction
+	    - LP_COUNT core reg
+	    - LP_START, LP_END aux regs
+	  This optional removes any use of ZOL instructions/regs from code
+
 config ARC_USE_UNALIGNED_MEM_ACCESS
 	bool "Enable unaligned access in HW"
 	default y
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index efc54f3e35e0..ec0f672bcee6 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -39,6 +39,7 @@  LINUXINCLUDE	+=  -include $(srctree)/arch/arc/include/asm/current.h
 endif
 
 cflags-y				+= -fsection-anchors
+cflags-y				+= -Wa,-I$(srctree)/arch/arc/include
 
 cflags-$(CONFIG_ARC_HAS_LLSC)		+= -mlock
 cflags-$(CONFIG_ARC_HAS_SWAPE)		+= -mswape
diff --git a/arch/arc/include/asm/asm-macro-dbnz-emul.h b/arch/arc/include/asm/asm-macro-dbnz-emul.h
new file mode 100644
index 000000000000..8c89f4234408
--- /dev/null
+++ b/arch/arc/include/asm/asm-macro-dbnz-emul.h
@@ -0,0 +1,12 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * DBNZ emulation for ARCompact or earlier ARCv2 cores
+ * 2 byte short instructions used to keep code size same as 4 byte DBNZ.
+ * This warrants usage of r0-r3, r12-r15, gas barfs otherwise catching
+ * offenders immediately
+ */
+.macro DBNZR r, lbl
+	sub_s  \r, \r, 1
+	brne_s \r, 0, \lbl
+.endm
diff --git a/arch/arc/include/asm/asm-macro-dbnz.h b/arch/arc/include/asm/asm-macro-dbnz.h
new file mode 100644
index 000000000000..fe658d2eab51
--- /dev/null
+++ b/arch/arc/include/asm/asm-macro-dbnz.h
@@ -0,0 +1,8 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * DBNZ instruction introduced in ARCv2
+ */
+.macro DBNZR r, lbl
+	dbnz  \r, \lbl
+.endm
diff --git a/arch/arc/include/asm/assembler.h b/arch/arc/include/asm/assembler.h
new file mode 100644
index 000000000000..426488ef27d4
--- /dev/null
+++ b/arch/arc/include/asm/assembler.h
@@ -0,0 +1,29 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ASM_ARC_ASM_H
+#define __ASM_ARC_ASM_H 1
+
+#ifdef __ASSEMBLY__
+
+#ifdef CONFIG_ARC_LACKS_ZOL
+#include <asm/asm-macro-dbnz.h>
+#else
+#include <asm/asm-macro-dbnz-emul.h>
+#endif
+
+#else	/* !__ASSEMBLY__ */
+
+/*
+ * ARCv2 cores have both LPcc and DBNZ instructions (starting 3.5a release).
+ * But in this context, LP present implies DBNZ not available (ARCompact ISA)
+ * or just not desirable, so emulate DBNZ with base instructions.
+ */
+#ifdef CONFIG_ARC_LACKS_ZOL
+asm(".include \"asm/asm-macro-dbnz.h\"\n");
+#else
+asm(".include \"asm/asm-macro-dbnz-emul.h\"\n");
+#endif
+
+#endif	/* __ASSEMBLY__ */
+
+#endif