new file mode 100644
@@ -0,0 +1,32 @@
+From d91d3daf5de90e0118227d8ddcb7bb4ff40c1b91 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Wed, 31 May 2017 09:18:37 +0200
+Subject: arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module
+
+This patch add the dt node for the syscon register present on the
+Allwinner H3/H5
+
+Only two register are present in this syscon and the only one useful is
+the one dedicated to EMAC clock..
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm/boot/dts/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/sun8i-h3.dtsi
+@@ -140,6 +140,12 @@
+ #size-cells = <1>;
+ ranges;
+
++ syscon: syscon@1c00000 {
++ compatible = "allwinner,sun8i-h3-system-controller",
++ "syscon";
++ reg = <0x01c00000 0x1000>;
++ };
++
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun8i-h3-dma";
+ reg = <0x01c02000 0x1000>;
new file mode 100644
@@ -0,0 +1,67 @@
+From 0eba511a3cac29d6338b22b5b727f40cf8d163df Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Wed, 31 May 2017 09:18:38 +0200
+Subject: arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver
+
+The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000
+speed.
+
+This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree.
+SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 34 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+--- a/arch/arm/boot/dts/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/sun8i-h3.dtsi
+@@ -333,6 +333,14 @@
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
++ emac_rgmii_pins: emac0 {
++ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
++ "PD5", "PD7", "PD8", "PD9", "PD10",
++ "PD12", "PD13", "PD15", "PD16", "PD17";
++ function = "emac";
++ drive-strength = <40>;
++ };
++
+ i2c0_pins: i2c0 {
+ allwinner,pins = "PA11", "PA12";
+ allwinner,function = "i2c0";
+@@ -431,6 +439,32 @@
+ clocks = <&osc24M>;
+ };
+
++ emac: ethernet@1c30000 {
++ compatible = "allwinner,sun8i-h3-emac";
++ syscon = <&syscon>;
++ reg = <0x01c30000 0x104>;
++ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++ resets = <&ccu RST_BUS_EMAC>;
++ reset-names = "stmmaceth";
++ clocks = <&ccu CLK_BUS_EMAC>;
++ clock-names = "stmmaceth";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ mdio: mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ int_mii_phy: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ clocks = <&ccu CLK_BUS_EPHY>;
++ resets = <&ccu RST_BUS_EPHY>;
++ };
++ };
++ };
++
+ wdt0: watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
new file mode 100644
@@ -0,0 +1,40 @@
+From a9992f2dd1890112643a93d621ff5a4c97c55d53 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Wed, 31 May 2017 09:18:42 +0200
+Subject: arm: sun8i: orangepi-2: Enable dwmac-sun8i
+
+The dwmac-sun8i hardware is present on the Orange PI 2.
+It uses the internal PHY.
+
+This patch create the needed emac node.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+@@ -55,6 +55,7 @@
+ aliases {
+ serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
++ ethernet0 = &emac;
+ ethernet1 = &rtl8189;
+ };
+
+@@ -109,6 +110,13 @@
+ status = "okay";
+ };
+
++&emac {
++ phy-handle = <&int_mii_phy>;
++ phy-mode = "mii";
++ allwinner,leds-active-low;
++ status = "okay";
++};
++
+ &ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
new file mode 100644
@@ -0,0 +1,64 @@
+From 1dcd0095019aca7533eaeed9475d995a4eb30137 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Mon, 5 Jun 2017 21:21:26 +0200
+Subject: ARM: sun8i: orangepi-plus: Enable dwmac-sun8i
+
+The dwmac-sun8i hardware is present on the Orange PI plus.
+It uses an external PHY rtl8211e via RGMII.
+
+This patch create the needed regulator, emac and phy nodes.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 32 ++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+@@ -47,6 +47,20 @@
+ model = "Xunlong Orange Pi Plus / Plus 2";
+ compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
+
++ aliases {
++ ethernet0 = &emac;
++ };
++
++ reg_gmac_3v3: gmac-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "gmac-3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <100000>;
++ enable-active-high;
++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++ };
++
+ reg_usb3_vbus: usb3-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+@@ -64,6 +78,24 @@
+ status = "okay";
+ };
+
++&emac {
++ pinctrl-names = "default";
++ pinctrl-0 = <&emac_rgmii_pins>;
++ phy-supply = <®_gmac_3v3>;
++ phy-handle = <&ext_rgmii_phy>;
++ phy-mode = "rgmii";
++
++ allwinner,leds-active-low;
++ status = "okay";
++};
++
++&mdio {
++ ext_rgmii_phy: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0>;
++ };
++};
++
+ &mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
new file mode 100644
@@ -0,0 +1,26 @@
+From 072b6e3692532b6281bf781ded1c7a986ac17471 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Thu, 6 Jul 2017 10:53:34 +0200
+Subject: ARM: dts: sunxi: h3/h5: Correct emac register size
+
+The datasheet said that emac register size is 0x10000 not 0x104
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+[wens@csie.org: Fixed commit subject prefix]
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+---
+ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/sun8i-h3.dtsi
+@@ -442,7 +442,7 @@
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+- reg = <0x01c30000 0x104>;
++ reg = <0x01c30000 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
This adds the device tree changes needed to make the GMAC stmmac driver working for the Allwinner H3 SoCs. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> --- ...unxi-h3-h5-Add-dt-node-for-the-syscon-con.patch | 32 +++++++++++ ...unxi-h3-h5-add-dwmac-sun8i-ethernet-drive.patch | 67 ++++++++++++++++++++++ ...2-arm-sun8i-orangepi-2-Enable-dwmac-sun8i.patch | 40 +++++++++++++ ...RM-sun8i-orangepi-plus-Enable-dwmac-sun8i.patch | 64 +++++++++++++++++++++ ...ts-sunxi-h3-h5-Correct-emac-register-size.patch | 26 +++++++++ 5 files changed, 229 insertions(+) create mode 100644 target/linux/sunxi/patches-4.9/0070-arm-sun8i-sunxi-h3-h5-Add-dt-node-for-the-syscon-con.patch create mode 100644 target/linux/sunxi/patches-4.9/0071-arm-sun8i-sunxi-h3-h5-add-dwmac-sun8i-ethernet-drive.patch create mode 100644 target/linux/sunxi/patches-4.9/0072-arm-sun8i-orangepi-2-Enable-dwmac-sun8i.patch create mode 100644 target/linux/sunxi/patches-4.9/0073-ARM-sun8i-orangepi-plus-Enable-dwmac-sun8i.patch create mode 100644 target/linux/sunxi/patches-4.9/0074-ARM-dts-sunxi-h3-h5-Correct-emac-register-size.patch