diff mbox series

[v2,2/3] KVM: selftests: Add RISC-V Sv57 page table indexing

Message ID 20260811230316.218770-3-jinyu.tang@linux.dev
State New
Headers show
Series KVM: riscv: Add KVM_PRE_FAULT_MEMORY support | expand

Commit Message

Jinyu Tang Aug. 11, 2026, 11:03 p.m. UTC
RISC-V selftests can create guests with five page-table levels, for
example when the selected guest mode is Sv57. The RISC-V page-table
walker only had index arrays for levels 0 through 3, so
virt_arch_pg_map() indexed past the end of the arrays when level 4 was
used.

Add the missing L4 index mask and shift so selftests can build guest
page tables for Sv57 VMs.

Signed-off-by: Jinyu Tang <jinyu.tang@linux.dev>
---
 tools/testing/selftests/kvm/include/riscv/processor.h | 3 +++
 tools/testing/selftests/kvm/lib/riscv/processor.c     | 2 ++
 2 files changed, 5 insertions(+)

Comments

Nutty.Liu Aug. 12, 2026, 12:22 p.m. UTC | #1
On 8/12/2026 7:03 AM, Jinyu Tang wrote:
> RISC-V selftests can create guests with five page-table levels, for
> example when the selected guest mode is Sv57. The RISC-V page-table
> walker only had index arrays for levels 0 through 3, so
> virt_arch_pg_map() indexed past the end of the arrays when level 4 was
> used.
>
> Add the missing L4 index mask and shift so selftests can build guest
> page tables for Sv57 VMs.
>
> Signed-off-by: Jinyu Tang <jinyu.tang@linux.dev>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty
> ---
>   tools/testing/selftests/kvm/include/riscv/processor.h | 3 +++
>   tools/testing/selftests/kvm/lib/riscv/processor.c     | 2 ++
>   2 files changed, 5 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
> index e3acf2ae9881..abde3c71c891 100644
> --- a/tools/testing/selftests/kvm/include/riscv/processor.h
> +++ b/tools/testing/selftests/kvm/include/riscv/processor.h
> @@ -127,6 +127,9 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handl
>   
>   void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handler);
>   
> +/* L4 index Bit[56:48] */
> +#define PGTBL_L4_INDEX_MASK			0x01FF000000000000ULL
> +#define PGTBL_L4_INDEX_SHIFT			48
>   /* L3 index Bit[47:39] */
>   #define PGTBL_L3_INDEX_MASK			0x0000FF8000000000ULL
>   #define PGTBL_L3_INDEX_SHIFT			39
> diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
> index ded5429f3448..b4d41a407553 100644
> --- a/tools/testing/selftests/kvm/lib/riscv/processor.c
> +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
> @@ -43,6 +43,7 @@ static u64 pte_index_mask[] = {
>   	PGTBL_L1_INDEX_MASK,
>   	PGTBL_L2_INDEX_MASK,
>   	PGTBL_L3_INDEX_MASK,
> +	PGTBL_L4_INDEX_MASK,
>   };
>   
>   static u32 pte_index_shift[] = {
> @@ -50,6 +51,7 @@ static u32 pte_index_shift[] = {
>   	PGTBL_L1_INDEX_SHIFT,
>   	PGTBL_L2_INDEX_SHIFT,
>   	PGTBL_L3_INDEX_SHIFT,
> +	PGTBL_L4_INDEX_SHIFT,
>   };
>   
>   static u64 pte_index(struct kvm_vm *vm, gva_t gva, int level)
diff mbox series

Patch

diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
index e3acf2ae9881..abde3c71c891 100644
--- a/tools/testing/selftests/kvm/include/riscv/processor.h
+++ b/tools/testing/selftests/kvm/include/riscv/processor.h
@@ -127,6 +127,9 @@  void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handl
 
 void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handler);
 
+/* L4 index Bit[56:48] */
+#define PGTBL_L4_INDEX_MASK			0x01FF000000000000ULL
+#define PGTBL_L4_INDEX_SHIFT			48
 /* L3 index Bit[47:39] */
 #define PGTBL_L3_INDEX_MASK			0x0000FF8000000000ULL
 #define PGTBL_L3_INDEX_SHIFT			39
diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
index ded5429f3448..b4d41a407553 100644
--- a/tools/testing/selftests/kvm/lib/riscv/processor.c
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -43,6 +43,7 @@  static u64 pte_index_mask[] = {
 	PGTBL_L1_INDEX_MASK,
 	PGTBL_L2_INDEX_MASK,
 	PGTBL_L3_INDEX_MASK,
+	PGTBL_L4_INDEX_MASK,
 };
 
 static u32 pte_index_shift[] = {
@@ -50,6 +51,7 @@  static u32 pte_index_shift[] = {
 	PGTBL_L1_INDEX_SHIFT,
 	PGTBL_L2_INDEX_SHIFT,
 	PGTBL_L3_INDEX_SHIFT,
+	PGTBL_L4_INDEX_SHIFT,
 };
 
 static u64 pte_index(struct kvm_vm *vm, gva_t gva, int level)