[v4,04/10] riscv: Introduce Zalasr instructions

Message ID	20251020042056.30283-5-luxu.kernel@bytedance.com
State	New
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Xu Lu <luxu.kernel@bytedance.com> To: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com, mark.rutland@arm.com, anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com, shuah@kernel.org, parri.andrea@gmail.com, ajones@ventanamicro.com, brs@rivosinc.com, guoren@kernel.org Cc: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, apw@canonical.com, joe@perches.com, lukas.bulwahn@gmail.com, Xu Lu <luxu.kernel@bytedance.com> Subject: [PATCH v4 04/10] riscv: Introduce Zalasr instructions Date: Mon, 20 Oct 2025 12:20:50 +0800 Message-ID: <20251020042056.30283-5-luxu.kernel@bytedance.com> In-Reply-To: <20251020042056.30283-1-luxu.kernel@bytedance.com> References: <20251020042056.30283-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 preview: Introduce l{b\|h\|w\|d}.{aq\|aqrl} and s{b\|h\|w\|d}.{rl\|aqrl} instruction encodings. Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> --- arch/riscv/include/asm/insn-def.h \| 79 +++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:533 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	riscv: Add Zalasr ISA extension support \| expand [v4,00/10] riscv: Add Zalasr ISA extension support [v4,01/10] riscv: Add ISA extension parsing for Zalasr [v4,02/10] dt-bindings: riscv: Add Zalasr ISA extension description [v4,03/10] riscv: hwprobe: Export Zalasr extension [v4,04/10] riscv: Introduce Zalasr instructions [v4,05/10] riscv: Apply Zalasr to smp_load_acquire/smp_store_release [v4,06/10] riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations [v4,07/10] riscv: Apply acquire/release semantics to arch_atomic operations [v4,08/10] riscv: Remove arch specific __atomic_acquire/release_fence [v4,09/10] RISC-V: KVM: Allow Zalasr extensions for Guest/VM [v4,10/10] RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test

Message ID

20251020042056.30283-5-luxu.kernel@bytedance.com

State

New

Headers

From: Xu Lu <luxu.kernel@bytedance.com>
To: corbet@lwn.net,
	paul.walmsley@sifive.com,
	palmer@dabbelt.com,
	aou@eecs.berkeley.edu,
	alex@ghiti.fr,
	robh@kernel.org,
	krzk+dt@kernel.org,
	conor+dt@kernel.org,
	will@kernel.org,
	peterz@infradead.org,
	boqun.feng@gmail.com,
	mark.rutland@arm.com,
	anup@brainfault.org,
	atish.patra@linux.dev,
	pbonzini@redhat.com,
	shuah@kernel.org,
	parri.andrea@gmail.com,
	ajones@ventanamicro.com,
	brs@rivosinc.com,
	guoren@kernel.org
Cc: linux-doc@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org,
	kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org,
	linux-kselftest@vger.kernel.org,
	apw@canonical.com,
	joe@perches.com,
	lukas.bulwahn@gmail.com,
	Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH v4 04/10] riscv: Introduce Zalasr instructions
Date: Mon, 20 Oct 2025 12:20:50 +0800
Message-ID: <20251020042056.30283-5-luxu.kernel@bytedance.com>
In-Reply-To: <20251020042056.30283-1-luxu.kernel@bytedance.com>
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Series

riscv: Add Zalasr ISA extension support | expand

Introduce l{b|h|w|d}.{aq|aqrl} and s{b|h|w|d}.{rl|aqrl} instruction encodings. Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> --- arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+)

Comments

Guo Ren Oct. 20, 2025, 1:34 p.m. UTC | #1

On Mon, Oct 20, 2025 at 12:21 PM Xu Lu <luxu.kernel@bytedance.com> wrote:
>
> Introduce l{b|h|w|d}.{aq|aqrl} and s{b|h|w|d}.{rl|aqrl} instruction
> encodings.
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---
>  arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++++++++++++++
>  1 file changed, 79 insertions(+)
>
> diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
> index d5adbaec1d010..3fec7e66ce50f 100644
> --- a/arch/riscv/include/asm/insn-def.h
> +++ b/arch/riscv/include/asm/insn-def.h
> @@ -179,6 +179,7 @@
>  #define RV___RS1(v)            __RV_REG(v)
>  #define RV___RS2(v)            __RV_REG(v)
>
> +#define RV_OPCODE_AMO          RV_OPCODE(47)
>  #define RV_OPCODE_MISC_MEM     RV_OPCODE(15)
>  #define RV_OPCODE_OP_IMM       RV_OPCODE(19)
>  #define RV_OPCODE_SYSTEM       RV_OPCODE(115)
> @@ -208,6 +209,84 @@
>         __ASM_STR(.error "hlv.d requires 64-bit support")
>  #endif
>
> +#define LB_AQ(dest, addr)                                      \
> +       INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26),                 \
> +              RD(dest), RS1(addr), __RS2(0))
> +
> +#define LB_AQRL(dest, addr)                                    \
> +       INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27),                 \
> +              RD(dest), RS1(addr), __RS2(0))
> +
> +#define LH_AQ(dest, addr)                                      \
> +       INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26),                 \
> +              RD(dest), RS1(addr), __RS2(0))
> +
> +#define LH_AQRL(dest, addr)                                    \
> +       INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27),                 \
> +              RD(dest), RS1(addr), __RS2(0))
> +
> +#define LW_AQ(dest, addr)                                      \
> +       INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26),                 \
> +              RD(dest), RS1(addr), __RS2(0))
> +
> +#define LW_AQRL(dest, addr)                                    \
> +       INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27),                 \
> +              RD(dest), RS1(addr), __RS2(0))
> +
> +#define SB_RL(src, addr)                                       \
> +       INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29),                 \
> +              __RD(0), RS1(addr), RS2(src))
> +
> +#define SB_AQRL(src, addr)                                     \
> +       INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31),                 \
> +              __RD(0), RS1(addr), RS2(src))
> +
> +#define SH_RL(src, addr)                                       \
> +       INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29),                 \
> +              __RD(0), RS1(addr), RS2(src))
> +
> +#define SH_AQRL(src, addr)                                     \
> +       INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31),                 \
> +              __RD(0), RS1(addr), RS2(src))
> +
> +#define SW_RL(src, addr)                                       \
> +       INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29),                 \
> +              __RD(0), RS1(addr), RS2(src))
> +
> +#define SW_AQRL(src, addr)                                     \
> +       INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31),                 \
> +              __RD(0), RS1(addr), RS2(src))
> +
> +#ifdef CONFIG_64BIT
> +#define LD_AQ(dest, addr)                                      \
> +       INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26),                 \
> +              RD(dest), RS1(addr), __RS2(0))
> +
> +#define LD_AQRL(dest, addr)                                    \
> +       INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27),                 \
> +              RD(dest), RS1(addr), __RS2(0))
> +
> +#define SD_RL(src, addr)                                       \
> +       INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29),                 \
> +              __RD(0), RS1(addr), RS2(src))
> +
> +#define SD_AQRL(src, addr)                                     \
> +       INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31),                 \
> +              __RD(0), RS1(addr), RS2(src))
> +#else
> +#define LD_AQ(dest, addr)                                      \
> +       __ASM_STR(.error "ld.aq requires 64-bit support")
> +
> +#define LD_AQRL(dest, addr)                                    \
> +       __ASM_STR(.error "ld.aqrl requires 64-bit support")
> +
> +#define SD_RL(dest, addr)                                      \
> +       __ASM_STR(.error "sd.rl requires 64-bit support")
> +
> +#define SD_AQRL(dest, addr)                                    \
> +       __ASM_STR(.error "sd.aqrl requires 64-bit support")
> +#endif
> +
>  #define SINVAL_VMA(vaddr, asid)                                        \
>         INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11),              \
>                __RD(0), RS1(vaddr), RS2(asid))
> --
> 2.20.1
>
I didn't find problem.

Reviewed-by: Guo Ren <guoren@kernel.org>

diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
index d5adbaec1d010..3fec7e66ce50f 100644
--- a/arch/riscv/include/asm/insn-def.h
+++ b/arch/riscv/include/asm/insn-def.h
@@ -179,6 +179,7 @@ 
 #define RV___RS1(v)		__RV_REG(v)
 #define RV___RS2(v)		__RV_REG(v)
 
+#define RV_OPCODE_AMO		RV_OPCODE(47)
 #define RV_OPCODE_MISC_MEM	RV_OPCODE(15)
 #define RV_OPCODE_OP_IMM	RV_OPCODE(19)
 #define RV_OPCODE_SYSTEM	RV_OPCODE(115)
@@ -208,6 +209,84 @@ 
 	__ASM_STR(.error "hlv.d requires 64-bit support")
 #endif
 
+#define LB_AQ(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LB_AQRL(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LH_AQ(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LH_AQRL(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LW_AQ(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LW_AQRL(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define SB_RL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SB_AQRL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SH_RL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SH_AQRL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SW_RL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SW_AQRL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#ifdef CONFIG_64BIT
+#define LD_AQ(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LD_AQRL(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define SD_RL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SD_AQRL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31),			\
+	       __RD(0), RS1(addr), RS2(src))
+#else
+#define LD_AQ(dest, addr)					\
+	__ASM_STR(.error "ld.aq requires 64-bit support")
+
+#define LD_AQRL(dest, addr)					\
+	__ASM_STR(.error "ld.aqrl requires 64-bit support")
+
+#define SD_RL(dest, addr)					\
+	__ASM_STR(.error "sd.rl requires 64-bit support")
+
+#define SD_AQRL(dest, addr)					\
+	__ASM_STR(.error "sd.aqrl requires 64-bit support")
+#endif
+
 #define SINVAL_VMA(vaddr, asid)					\
 	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11),		\
 	       __RD(0), RS1(vaddr), RS2(asid))

[v4,04/10] riscv: Introduce Zalasr instructions

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