[RFC,v2,16/18] vfio: enable IOMMU_TYPE1 for RISC-V

Message ID	20250920203851.2205115-36-ajones@ventanamicro.com
State	New
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Andrew Jones <ajones@ventanamicro.com> To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: jgg@nvidia.com, zong.li@sifive.com, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atish.patra@linux.dev, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, alex@ghiti.fr Subject: [RFC PATCH v2 16/18] vfio: enable IOMMU_TYPE1 for RISC-V Date: Sat, 20 Sep 2025 15:39:06 -0500 Message-ID: <20250920203851.2205115-36-ajones@ventanamicro.com> In-Reply-To: <20250920203851.2205115-20-ajones@ventanamicro.com> References: <20250920203851.2205115-20-ajones@ventanamicro.com> MIME-Version: 1.0 preview: From: Tomasz Jeznach <tjeznach@rivosinc.com> Enable VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- drivers/vfio/Kconfig \| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Content analysis details: (-2.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:135 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	iommu/riscv: Add irqbypass support \| expand [RFC,v2,00/18] iommu/riscv: Add irqbypass support [RFC,v2,01/18] genirq/msi: Provide DOMAIN_BUS_MSI_REMAP [RFC,v2,02/18] iommu/riscv: Move struct riscv_iommu_domain and info to iommu.h [RFC,v2,03/18] iommu/riscv: Use data structure instead of individual values [RFC,v2,04/18] iommu/riscv: Add IRQ domain for interrupt remapping [RFC,v2,05/18] iommu/riscv: Prepare to use MSI table [RFC,v2,06/18] iommu/riscv: Implement MSI table management functions [RFC,v2,07/18] iommu/riscv: Export phys_to_ppn and ppn_to_phys [RFC,v2,08/18] iommu/riscv: Use MSI table to enable IMSIC access [RFC,v2,09/18] iommu/dma: enable IOMMU_DMA for RISC-V [RFC,v2,10/18] RISC-V: Define irqbypass vcpu_info [RFC,v2,11/18] iommu/riscv: Maintain each irq msitbl index with chip data [RFC,v2,12/18] iommu/riscv: Add guest file irqbypass support [RFC,v2,13/18] iommu/riscv: report iommu capabilities [RFC,v2,14/18] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch [RFC,v2,15/18] RISC-V: KVM: Add guest file irqbypass support [RFC,v2,16/18] vfio: enable IOMMU_TYPE1 for RISC-V [RFC,v2,17/18] RISC-V: defconfig: Add VFIO modules [RFC,v2,18/18] DO NOT UPSTREAM: RISC-V: KVM: Workaround kvm_riscv_gstage_ioremap() bug

Message ID

20250920203851.2205115-36-ajones@ventanamicro.com

State

New

Headers

From: Andrew Jones <ajones@ventanamicro.com>
To: iommu@lists.linux.dev,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: jgg@nvidia.com,
	zong.li@sifive.com,
	tjeznach@rivosinc.com,
	joro@8bytes.org,
	will@kernel.org,
	robin.murphy@arm.com,
	anup@brainfault.org,
	atish.patra@linux.dev,
	tglx@linutronix.de,
	alex.williamson@redhat.com,
	paul.walmsley@sifive.com,
	palmer@dabbelt.com,
	alex@ghiti.fr
Subject: [RFC PATCH v2 16/18] vfio: enable IOMMU_TYPE1 for RISC-V
Date: Sat, 20 Sep 2025 15:39:06 -0500
Message-ID: <20250920203851.2205115-36-ajones@ventanamicro.com>
In-Reply-To: <20250920203851.2205115-20-ajones@ventanamicro.com>
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Series

iommu/riscv: Add irqbypass support | expand

Commit Message

Andrew Jones Sept. 20, 2025, 8:39 p.m. UTC

From: Tomasz Jeznach <tjeznach@rivosinc.com>

Enable VFIO support on RISC-V architecture.

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
 drivers/vfio/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Nutty.Liu Oct. 5, 2025, 8:44 a.m. UTC | #1

On 9/21/2025 4:39 AM, Andrew Jones wrote:
> From: Tomasz Jeznach <tjeznach@rivosinc.com>
>
> Enable VFIO support on RISC-V architecture.
>
> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>   drivers/vfio/Kconfig | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty
> diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
> index ceae52fd7586..ad62205b4e45 100644
> --- a/drivers/vfio/Kconfig
> +++ b/drivers/vfio/Kconfig
> @@ -39,7 +39,7 @@ config VFIO_GROUP
>   
>   config VFIO_CONTAINER
>   	bool "Support for the VFIO container /dev/vfio/vfio"
> -	select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
> +	select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV)
>   	depends on VFIO_GROUP
>   	default y
>   	help

diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
index ceae52fd7586..ad62205b4e45 100644
--- a/drivers/vfio/Kconfig
+++ b/drivers/vfio/Kconfig
@@ -39,7 +39,7 @@  config VFIO_GROUP
 
 config VFIO_CONTAINER
 	bool "Support for the VFIO container /dev/vfio/vfio"
-	select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
+	select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV)
 	depends on VFIO_GROUP
 	default y
 	help

[RFC,v2,16/18] vfio: enable IOMMU_TYPE1 for RISC-V

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