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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4a75ee5a5sm13529305a91.17.2024.06.18.10.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:32:21 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH 3/4] riscv: Add methods to toggle interrupt enable bits Date: Wed, 19 Jun 2024 01:30:52 +0800 Message-ID: <20240618173053.364776-4-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240618173053.364776-1-jamestiotio@gmail.com> References: <20240618173053.364776-1-jamestiotio@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240618_103224_217949_E85EA0EA X-CRM114-Status: GOOD ( 13.24 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add some helper methods to toggle the interrupt enable bits in the SIE register. Signed-off-by: James Raphael Tiovalen --- riscv/Makefile | 1 + lib/riscv/asm/csr.h | 7 +++++++ lib/riscv/asm/interrupt.h | 12 ++++++++++++ lib/riscv/interrupt.c | 39 ++++++++++++++++++++++++++++++++ [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [jamestiotio(at)gmail.com] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102b listed in] [list.dnswl.org] -0.0 T_SCC_BODY_TEXT_LINE No description available. X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add some helper methods to toggle the interrupt enable bits in the SIE register. Signed-off-by: James Raphael Tiovalen --- riscv/Makefile | 1 + lib/riscv/asm/csr.h | 7 +++++++ lib/riscv/asm/interrupt.h | 12 ++++++++++++ lib/riscv/interrupt.c | 39 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 lib/riscv/asm/interrupt.h create mode 100644 lib/riscv/interrupt.c diff --git a/riscv/Makefile b/riscv/Makefile index 919a3ebb..108d4481 100644 --- a/riscv/Makefile +++ b/riscv/Makefile @@ -30,6 +30,7 @@ cflatobjs += lib/memregions.o cflatobjs += lib/on-cpus.o cflatobjs += lib/vmalloc.o cflatobjs += lib/riscv/bitops.o +cflatobjs += lib/riscv/interrupt.o cflatobjs += lib/riscv/io.o cflatobjs += lib/riscv/isa.o cflatobjs += lib/riscv/mmu.o diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index c1777744..da58b0ce 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -4,15 +4,22 @@ #include #define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 #define CSR_STVAL 0x143 +#define CSR_SIP 0x144 #define CSR_SATP 0x180 #define SSTATUS_SIE (_AC(1, UL) << 1) +#define SIE_SSIE (_AC(1, UL) << 1) +#define SIE_STIE (_AC(1, UL) << 5) +#define SIE_SEIE (_AC(1, UL) << 9) +#define SIE_LCOFIE (_AC(1, UL) << 13) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) diff --git a/lib/riscv/asm/interrupt.h b/lib/riscv/asm/interrupt.h new file mode 100644 index 00000000..b760afbb --- /dev/null +++ b/lib/riscv/asm/interrupt.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASMRISCV_INTERRUPT_H_ +#define _ASMRISCV_INTERRUPT_H_ + +#include + +void toggle_software_interrupt(bool enable); +void toggle_timer_interrupt(bool enable); +void toggle_external_interrupt(bool enable); +void toggle_local_cof_interrupt(bool enable); + +#endif /* _ASMRISCV_INTERRUPT_H_ */ diff --git a/lib/riscv/interrupt.c b/lib/riscv/interrupt.c new file mode 100644 index 00000000..bc0e16f1 --- /dev/null +++ b/lib/riscv/interrupt.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024, James Raphael Tiovalen + */ +#include +#include +#include + +void toggle_software_interrupt(bool enable) +{ + if (enable) + csr_set(CSR_SIE, SIE_SSIE); + else + csr_clear(CSR_SIE, SIE_SSIE); +} + +void toggle_timer_interrupt(bool enable) +{ + if (enable) + csr_set(CSR_SIE, SIE_STIE); + else + csr_clear(CSR_SIE, SIE_STIE); +} + +void toggle_external_interrupt(bool enable) +{ + if (enable) + csr_set(CSR_SIE, SIE_SEIE); + else + csr_clear(CSR_SIE, SIE_SEIE); +} + +void toggle_local_cof_interrupt(bool enable) +{ + if (enable) + csr_set(CSR_SIE, SIE_LCOFIE); + else + csr_clear(CSR_SIE, SIE_LCOFIE); +}