[kvmtool,v2,08/10] riscv: Add Zvfh[min] extensions support

Message ID	20240325153141.6816-9-apatel@ventanamicro.com
State	Accepted
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Anup Patel <apatel@ventanamicro.com> To: Will Deacon <will@kernel.org>, julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel <apatel@ventanamicro.com> Subject: [kvmtool PATCH v2 08/10] riscv: Add Zvfh[min] extensions support Date: Mon, 25 Mar 2024 21:01:39 +0530 Message-Id: <20240325153141.6816-9-apatel@ventanamicro.com> In-Reply-To: <20240325153141.6816-1-apatel@ventanamicro.com> References: <20240325153141.6816-1-apatel@ventanamicro.com> MIME-Version: 1.0 preview: When the Zvfh[min] extensions are available expose it to the guest via device tree so that guest can use it. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> --- riscv/fdt.c \| 2 ++ riscv/include/kvm/kvm-config-arch.h \| 6 ++++++ 2 files changed, 8 inserti [...] Content analysis details: (3.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:636 listed in] [list.dnswl.org] 3.6 RCVD_IN_SBL_CSS RBL: Received via a relay in Spamhaus SBL-CSS [171.76.87.36 listed in zen.spamhaus.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	More ISA extensions \| expand [kvmtool,v2,00/10] More ISA extensions [kvmtool,v2,01/10] Sync-up headers with Linux-6.8 for KVM RISC-V [kvmtool,v2,02/10] kvmtool: Fix absence of __packed definition [kvmtool,v2,03/10] riscv: Add Zbc extension support [kvmtool,v2,04/10] riscv: Add scalar crypto extensions support [kvmtool,v2,05/10] riscv: Add vector crypto extensions support [kvmtool,v2,06/10] riscv: Add Zfh[min] extensions support [kvmtool,v2,07/10] riscv: Add Zihintntl extension support [kvmtool,v2,08/10] riscv: Add Zvfh[min] extensions support [kvmtool,v2,09/10] riscv: Add Zfa extensiona support [kvmtool,v2,10/10] riscv: Allow disabling SBI STA extension for Guest

Message ID

20240325153141.6816-9-apatel@ventanamicro.com

State

Accepted

Headers

From: Anup Patel <apatel@ventanamicro.com>
To: Will Deacon <will@kernel.org>,
	julien.thierry.kdev@gmail.com,
	maz@kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Atish Patra <atishp@atishpatra.org>,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [kvmtool PATCH v2 08/10] riscv: Add Zvfh[min] extensions support
Date: Mon, 25 Mar 2024 21:01:39 +0530
Message-Id: <20240325153141.6816-9-apatel@ventanamicro.com>
In-Reply-To: <20240325153141.6816-1-apatel@ventanamicro.com>
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Series

More ISA extensions | expand

Commit Message

Anup Patel March 25, 2024, 3:31 p.m. UTC

When the Zvfh[min] extensions are available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 riscv/fdt.c                         | 2 ++
 riscv/include/kvm/kvm-config-arch.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 80e045d..005301e 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -49,6 +49,8 @@  struct isa_ext_info isa_info_arr[] = {
 	{"zkt", KVM_RISCV_ISA_EXT_ZKT},
 	{"zvbb", KVM_RISCV_ISA_EXT_ZVBB},
 	{"zvbc", KVM_RISCV_ISA_EXT_ZVBC},
+	{"zvfh", KVM_RISCV_ISA_EXT_ZVFH},
+	{"zvfhmin", KVM_RISCV_ISA_EXT_ZVFHMIN},
 	{"zvkb", KVM_RISCV_ISA_EXT_ZVKB},
 	{"zvkg", KVM_RISCV_ISA_EXT_ZVKG},
 	{"zvkned", KVM_RISCV_ISA_EXT_ZVKNED},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 2935c01..10ca3b8 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -124,6 +124,12 @@  struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zvbc",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVBC],	\
 		    "Disable Zvbc Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvfh",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVFH],	\
+		    "Disable Zvfh Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zvfhmin",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVFHMIN],	\
+		    "Disable Zvfhmin Extension"),			\
 	OPT_BOOLEAN('\0', "disable-zvkb",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZVKB],	\
 		    "Disable Zvkb Extension"),				\

[kvmtool,v2,08/10] riscv: Add Zvfh[min] extensions support

Commit Message

Patch