[4/6] riscv: Implement test for architecture ID register

Message ID	20240313215106.325766-5-cem@kernel.org
State	Handled Elsewhere
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: cem@kernel.org To: kvm-riscv@lists.infradead.org Cc: ajones@ventanamicro.com Subject: [PATCH 4/6] riscv: Implement test for architecture ID register Date: Wed, 13 Mar 2024 22:50:55 +0100 Message-ID: <20240313215106.325766-5-cem@kernel.org> In-Reply-To: <20240313215106.325766-1-cem@kernel.org> References: <20240313215106.325766-1-cem@kernel.org> MIME-Version: 1.0 preview: From: Carlos Maiolino <cem@kernel.org> Probe the MARCHID register and compare it to the specified MARCHID environment variable. Signed-off-by: Carlos Maiolino <cmaiolino@redhat.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> --- riscv/sbi.c \| 8 ++++++++ 1 file changed, 8 insertions(+) Content analysis details: (-6.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [139.178.84.217 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 T_SCC_BODY_TEXT_LINE No description available. -1.0 DKIMWL_WL_HIGH DKIMwl.org - High trust sender Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	Add riscv tests to cover the base extension specs \| expand [V4,0/6] Add riscv tests to cover the base extension specs [V4,1/6] riscv: Add a wrapper to call sbi_ecall for base extension [V4,2/6] riscv: Add test to probe SBI Extension [V4,3/6] riscv: Factor out environment variable check and report generation [4/6] riscv: Implement test for architecture ID register [V4,5/6] riscv: Enable gen_report() to print the wrong value in case of failure [V4,6/6] riscv: Test for specific SBI implementation ID

Message ID

20240313215106.325766-5-cem@kernel.org

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Handled Elsewhere

Headers

From: cem@kernel.org
To: kvm-riscv@lists.infradead.org
Cc: ajones@ventanamicro.com
Subject: [PATCH 4/6] riscv: Implement test for architecture ID register
Date: Wed, 13 Mar 2024 22:50:55 +0100
Message-ID: <20240313215106.325766-5-cem@kernel.org>
In-Reply-To: <20240313215106.325766-1-cem@kernel.org>
References: <20240313215106.325766-1-cem@kernel.org>
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Series

Add riscv tests to cover the base extension specs | expand

Commit Message

Carlos Maiolino March 13, 2024, 9:50 p.m. UTC

From: Carlos Maiolino <cem@kernel.org>

Probe the MARCHID register and compare it to the specified MARCHID
environment variable.

Signed-off-by: Carlos Maiolino <cmaiolino@redhat.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 riscv/sbi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/riscv/sbi.c b/riscv/sbi.c
index 6be78dae..f33c19f4 100644
--- a/riscv/sbi.c
+++ b/riscv/sbi.c
@@ -56,6 +56,14 @@  static void check_base(void)
 	gen_report(&ret, expected);
 	report_prefix_pop();
 
+	report_prefix_push("marchid");
+	if (env_or_skip("MARCHID")) {
+		expected = strtol(getenv("MARCHID"), NULL, 0);
+		ret = __base_sbi_ecall(SBI_EXT_BASE_GET_MARCHID, 0);
+		gen_report(&ret, expected);
+	}
+	report_prefix_pop();
+
 	report_prefix_pop();
 }

[4/6] riscv: Implement test for architecture ID register

Commit Message

Patch