[v8,08/14] arm64: tlb: Implement __flush_s2_tlb_range_op()

Message ID	20230808231330.3855936-9-rananta@google.com
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Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> Date: Tue, 8 Aug 2023 23:13:24 +0000 In-Reply-To: <20230808231330.3855936-1-rananta@google.com> Mime-Version: 1.0 References: <20230808231330.3855936-1-rananta@google.com> Message-ID: <20230808231330.3855936-9-rananta@google.com> Subject: [PATCH v8 08/14] arm64: tlb: Implement __flush_s2_tlb_range_op() From: Raghavendra Rao Ananta <rananta@google.com> To: Oliver Upton <oliver.upton@linux.dev>, Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Paolo Bonzini <pbonzini@redhat.com>, Sean Christopherson <seanjc@google.com>, Huacai Chen <chenhuacai@kernel.org>, Zenghui Yu <yuzenghui@huawei.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Jing Zhang <jingzhangos@google.com>, Reiji Watanabe <reijiw@google.com>, Colton Lewis <coltonlewis@google.com>, Raghavendra Rao Anata <rananta@google.com>, David Matlack <dmatlack@google.com>, Fuad Tabba <tabba@google.com>, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org preview: Define __flush_s2_tlb_range_op(), as a wrapper over __flush_tlb_range_op(), for stage-2 specific range-based TLBI operations that doesn't necessarily have to deal with 'asid' and 'tlbi_user' arguments [...] Content analysis details: (-7.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:b4a listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -7.5 USER_IN_DEF_DKIM_WL From: address is in the default DKIM white-list -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 DKIMWL_WL_MED DKIMwl.org - Medium trust sender Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	KVM: arm64: Add support for FEAT_TLBIRANGE \| expand [v8,00/14] KVM: arm64: Add support for FEAT_TLBIRANGE [v8,01/14] KVM: Rename kvm_arch_flush_remote_tlb() to kvm_arch_flush_remote_tlbs() [v8,02/14] KVM: Declare kvm_arch_flush_remote_tlbs() globally [v8,03/14] KVM: arm64: Use kvm_arch_flush_remote_tlbs() [v8,04/14] KVM: Remove CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL [v8,05/14] KVM: Allow range-based TLB invalidation from common code [v8,06/14] KVM: Move kvm_arch_flush_remote_tlbs_memslot() to common code [v8,07/14] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range [v8,08/14] arm64: tlb: Implement __flush_s2_tlb_range_op() [v8,09/14] KVM: arm64: Implement __kvm_tlb_flush_vmid_range() [v8,10/14] KVM: arm64: Define kvm_tlb_flush_vmid_range() [v8,11/14] KVM: arm64: Implement kvm_arch_flush_remote_tlbs_range() [v8,12/14] KVM: arm64: Flush only the memslot after write-protect [v8,13/14] KVM: arm64: Invalidate the table entries upon a range [v8,14/14] KVM: arm64: Use TLBI range-based intructions for unmap

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20230808231330.3855936-9-rananta@google.com

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Date: Tue,  8 Aug 2023 23:13:24 +0000
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Message-ID: <20230808231330.3855936-9-rananta@google.com>
Subject: [PATCH v8 08/14] arm64: tlb: Implement __flush_s2_tlb_range_op()
From: Raghavendra Rao Ananta <rananta@google.com>
To: Oliver Upton <oliver.upton@linux.dev>, Marc Zyngier <maz@kernel.org>,
	James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
 Sean Christopherson <seanjc@google.com>,
	Huacai Chen <chenhuacai@kernel.org>, Zenghui Yu <yuzenghui@huawei.com>,
	Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>,
	Jing Zhang <jingzhangos@google.com>, Reiji Watanabe <reijiw@google.com>,
	Colton Lewis <coltonlewis@google.com>,
 Raghavendra Rao Anata <rananta@google.com>,
	David Matlack <dmatlack@google.com>, Fuad Tabba <tabba@google.com>,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org
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Series

KVM: arm64: Add support for FEAT_TLBIRANGE | expand

Commit Message

Raghavendra Rao Ananta Aug. 8, 2023, 11:13 p.m. UTC

Define __flush_s2_tlb_range_op(), as a wrapper over
__flush_tlb_range_op(), for stage-2 specific range-based TLBI
operations that doesn't necessarily have to deal with 'asid'
and 'tlbi_user' arguments.

Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
 arch/arm64/include/asm/tlbflush.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Shaoqin Huang Aug. 11, 2023, 3:16 a.m. UTC | #1

On 8/9/23 07:13, Raghavendra Rao Ananta wrote:
> Define __flush_s2_tlb_range_op(), as a wrapper over
> __flush_tlb_range_op(), for stage-2 specific range-based TLBI
> operations that doesn't necessarily have to deal with 'asid'
> and 'tlbi_user' arguments.
> 
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
Reviewed-by: Shaoqin Huang <shahuang@redhat.com>
> ---
>   arch/arm64/include/asm/tlbflush.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index b9475a852d5be..93f4b397f9a12 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -340,6 +340,9 @@ do {									\
>   	}								\
>   } while (0)
>   
> +#define __flush_s2_tlb_range_op(op, start, pages, stride, tlb_level) \
> +	__flush_tlb_range_op(op, start, pages, stride, 0, tlb_level, false)
> +
>   static inline void __flush_tlb_range(struct vm_area_struct *vma,
>   				     unsigned long start, unsigned long end,
>   				     unsigned long stride, bool last_level,

diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index b9475a852d5be..93f4b397f9a12 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -340,6 +340,9 @@  do {									\
 	}								\
 } while (0)
 
+#define __flush_s2_tlb_range_op(op, start, pages, stride, tlb_level) \
+	__flush_tlb_range_op(op, start, pages, stride, 0, tlb_level, false)
+
 static inline void __flush_tlb_range(struct vm_area_struct *vma,
 				     unsigned long start, unsigned long end,
 				     unsigned long stride, bool last_level,

[v8,08/14] arm64: tlb: Implement __flush_s2_tlb_range_op()

Commit Message

Comments

Patch