diff mbox series

[02/17] riscv: Extending cpufeature.c to detect V-extension

Message ID 20220921194629.1480202-3-stillson@rivosinc.com
State Superseded
Headers show
Series Prctl to enable vector commands, previous vector patches rebased | expand

Commit Message

Chris Stillson Sept. 21, 2022, 7:46 p.m. UTC 
From: Guo Ren <ren_guo@c-sky.com>

Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/uapi/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c      | 1 +
 2 files changed, 2 insertions(+)

Comments

Conor Dooley Sept. 21, 2022, 9:33 p.m. UTC | #1 
On Wed, Sep 21, 2022 at 09:11:56PM +0100, Conor Dooley wrote:
> On Wed, Sep 21, 2022 at 12:46:14PM -0700, Chris Stillson wrote:
> 
> Hey Chris,
> 
> Looks like this only partially made it to the list. The cover letter is
> missing as are a bunch of the patches in the middle, see:
> https://lore.kernel.org/linux-riscv/20220921194629.1480202-3-stillson@rivosinc.com/T/#t

nvm, rest of it seems to have finally made it through now.

> Also, when you run format-patch to generate the patches, please add the
> `-v` flag with a number so that the patchset gets the version number
> added to it.
> 
> Ohh, and Palmer's non-rivos email looks wrong?

Rest still applies though & rerolling as v12 would be nice so that the
tools don't get confused about which version is which since you've now
sent a pair of v1s.

Your SoB is still missing from the individual patches too.

Getting there though, this one is at least threaded & the patches are
not whitespace damaged/line wrapped anymore AFAICT.

Thanks,
Conor.
diff mbox series

Patch

diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index 46dc3f5ee99f..c52bb7bbbabe 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@ 
 #define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))
 #define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))
 #define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))
 
 #endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 553d755483ed..8d4448c2d4f4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -83,6 +83,7 @@  void __init riscv_fill_hwcap(void)
 	isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
 	isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
 	isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+	isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
 
 	elf_hwcap = 0;