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Wed, 21 Sep 2022 12:47:00 -0700 (PDT) From: Chris Stillson To: linux-riscv@lists.infradead.org, jpalmer@dabbelt.com, kvm-riscv@lists.infradead.org Cc: Vincent Chen , Greentime Hu Subject: [PATCH 15/17] riscv: Add V extension to KVM ISA allow list Date: Wed, 21 Sep 2022 12:46:27 -0700 Message-Id: <20220921194629.1480202-16-stillson@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220921194629.1480202-1-stillson@rivosinc.com> References: <20220921194629.1480202-1-stillson@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220921_124700_949331_B37C202F X-CRM114-Status: UNSURE ( 9.06 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Vincent Chen Add V extension to KVM_RISCV_ISA_ALLOWED list to enable VCPU to support V extension. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/hwcap.h | 1 + 1 file changed, 1 insertion(+) Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62a listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Vincent Chen Add V extension to KVM_RISCV_ISA_ALLOWED list to enable VCPU to support V extension. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/hwcap.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6f59ec64175e..b242ed155262 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -35,6 +35,7 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_m ('m' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') +#define RISCV_ISA_EXT_v ('v' - 'a') /* * Increse this to higher value as kernel support more ISA extensions.