From patchwork Fri Jan 26 14:23:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 1891350 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=QYM+N2Xz; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256 header.s=key1 header.b=wICAl9ld; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=198.137.202.133; helo=bombadil.infradead.org; envelope-from=kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TM0RQ69tGz23gJ for ; Sat, 27 Jan 2024 01:28:17 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=RA/aiOlqpV6r+H4JvPHqznXDxmNiYxViMszqTXAPtnI=; b=QYM+N2XzrxsMlL fTD6vPVR5x/ic/MNXsgZF8cdFM77U/2lYIqOpLhFsS9vVkUczDGfC1GoVKjkyKUkKIlvEO1bBAQH6 KWKhm6aRXRSQB2a1ZDfHMDMZfnhRwiNh2ONnrgfaur1YnsTfhzWSTegsenmbI4mykG9CJUPT1PIo4 OkG3k5vxenS1COl0OGqD8hJl9RfFEIDIR4MUnLDKp9M9zomk5QPx11dZ8f2dEit4XEE+PzS5mJDN5 6vFk1DiPbc6tDGFJAnlib2Y96BkhZGAdz4rO5NmhxmPApTj2f4NN37XO7MPD6UrVyrhkl2vNth7ST xz+Jom3j9qF4QUEjX5wg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rTN7O-00000004JWx-0qmQ; Fri, 26 Jan 2024 14:23:42 +0000 Received: from out-187.mta0.migadu.com ([2001:41d0:1004:224b::bb]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rTN7K-00000004JRI-2ga9 for kvm-riscv@lists.infradead.org; Fri, 26 Jan 2024 14:23:40 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1706279007; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=AGdZaxsblPPQTcb4MiCja5v9bc/JeD30lRJSlJeOJ4k=; b=wICAl9ld7yTz6MeEFnwdUtPTMXuJ/M1HUV0EZdrFjcZyixhEm80bgRfpX2IMy4hH8rLCym aBvV2H7lJfu3+LSsQ4A21osXNrstXCvTrsGYsUTBuOb/YHIUrL1+Rt8z1t/lUfho36cnVn 4rZisFWDGC0YHsG3F3lc/23kxGC2wQE= From: Andrew Jones To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, kvmarm@lists.linux.dev Cc: ajones@ventanamicro.com, anup@brainfault.org, atishp@atishpatra.org, pbonzini@redhat.com, thuth@redhat.com, alexandru.elisei@arm.com, eric.auger@redhat.com Subject: [kvm-unit-tests PATCH v2 00/24] Introduce RISC-V Date: Fri, 26 Jan 2024 15:23:25 +0100 Message-ID: <20240126142324.66674-26-andrew.jones@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240126_062339_189802_8851E439 X-CRM114-Status: GOOD ( 15.45 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: v2: - While basing [1] on this series I found two bugs (one in exception return and another in isa string parsing). I also decided to expose a get_pte() function to unit tests and also an isa-extensio [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 T_SCC_BODY_TEXT_LINE No description available. X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org v2: - While basing [1] on this series I found two bugs (one in exception return and another in isa string parsing). I also decided to expose a get_pte() function to unit tests and also an isa-extension-by-name function to check for arbitrary extensions. Finally, I picked up Thomas' gitlab-ci suggestion and his tags. (Having [1] and the selftests running makes me pretty happy with the series, so, unless somebody shouts, I'll merge this sometime next week.) [1] https://gitlab.com/jones-drew/kvm-unit-tests/-/commit/e9c6c58b1c799de77fd39970b358a7592ecd048f Thanks, drew Original cover letter follows: This series adds another architecture to kvm-unit-tests (RISC-V, both 32-bit and 64-bit). Much of the code is borrowed from arm/arm64 by mimicking its patterns or by first making the arm code more generic and moving it to the common lib. This series brings UART, SMP, MMU, and exception handling support. One should be able to start writing CPU validation tests in a mix of C and asm as well as write SBI tests, as is the plan for the SBI verification framework. kvm-unit-tests provides backtraces on asserts and input can be given to the tests through command line arguments, environment variables, and the DT (there's already an ISA string parser for extension detection). This series only targets QEMU TCG and KVM, but OpenSBI may be replaced with other SBI implementations, such as RustSBI. It's a goal to target bare-metal as soon as possible, so EFI support is already in progress and will be posted soon. More follow on series will come as well, bringing interrupt controller support for timer and PMU testing, support to run tests in usermode, and whatever else people need for their tests. Andrew Jones (24): configure: Add ARCH_LIBDIR riscv: Initial port, hello world arm/arm64: Move cpumask.h to common lib arm/arm64: Share cpu online, present and idle masks riscv: Add DT parsing riscv: Add initial SBI support riscv: Add run script and unittests.cfg riscv: Add riscv32 support riscv: Add exception handling riscv: Add backtrace support arm/arm64: Generalize wfe/sev names in smp.c arm/arm64: Remove spinlocks from on_cpu_async arm/arm64: Share on_cpus riscv: Compile with march riscv: Add SMP support arm/arm64: Share memregions riscv: Populate memregions and switch to page allocator riscv: Add MMU support riscv: Enable the MMU in secondaries riscv: Enable vmalloc lib: Add strcasecmp and strncasecmp riscv: Add isa string parsing gitlab-ci: Add riscv64 tests MAINTAINERS: Add riscv .gitlab-ci.yml | 17 +++ MAINTAINERS | 8 ++ Makefile | 2 +- arm/Makefile.common | 2 + arm/selftest.c | 3 +- configure | 16 +++ lib/arm/asm/gic-v2.h | 2 +- lib/arm/asm/gic-v3.h | 2 +- lib/arm/asm/gic.h | 2 +- lib/arm/asm/setup.h | 14 -- lib/arm/asm/smp.h | 45 +----- lib/arm/mmu.c | 3 +- lib/arm/setup.c | 93 +++---------- lib/arm/smp.c | 135 +----------------- lib/arm64/asm/cpumask.h | 1 - lib/{arm/asm => }/cpumask.h | 42 +++++- lib/ctype.h | 10 ++ lib/elf.h | 11 ++ lib/ldiv32.c | 16 +++ lib/linux/const.h | 2 + lib/memregions.c | 82 +++++++++++ lib/memregions.h | 29 ++++ lib/on-cpus.c | 154 +++++++++++++++++++++ lib/on-cpus.h | 14 ++ lib/riscv/.gitignore | 1 + lib/riscv/asm-offsets.c | 62 +++++++++ lib/riscv/asm/asm-offsets.h | 1 + lib/riscv/asm/barrier.h | 20 +++ lib/riscv/asm/bitops.h | 21 +++ lib/riscv/asm/bug.h | 20 +++ lib/riscv/asm/csr.h | 100 ++++++++++++++ lib/riscv/asm/io.h | 87 ++++++++++++ lib/riscv/asm/isa.h | 33 +++++ lib/riscv/asm/memory_areas.h | 1 + lib/riscv/asm/mmu.h | 32 +++++ lib/riscv/asm/page.h | 21 +++ lib/riscv/asm/pgtable.h | 42 ++++++ lib/riscv/asm/processor.h | 29 ++++ lib/riscv/asm/ptrace.h | 46 +++++++ lib/riscv/asm/sbi.h | 54 ++++++++ lib/riscv/asm/setup.h | 15 ++ lib/riscv/asm/smp.h | 29 ++++ lib/riscv/asm/spinlock.h | 7 + lib/riscv/asm/stack.h | 12 ++ lib/riscv/bitops.c | 47 +++++++ lib/riscv/io.c | 97 +++++++++++++ lib/riscv/isa.c | 126 +++++++++++++++++ lib/riscv/mmu.c | 205 +++++++++++++++++++++++++++ lib/riscv/processor.c | 64 +++++++++ lib/riscv/sbi.c | 40 ++++++ lib/riscv/setup.c | 188 +++++++++++++++++++++++++ lib/riscv/smp.c | 70 ++++++++++ lib/riscv/stack.c | 32 +++++ lib/string.c | 14 ++ lib/string.h | 2 + riscv/Makefile | 106 ++++++++++++++ riscv/cstart.S | 259 +++++++++++++++++++++++++++++++++++ riscv/flat.lds | 75 ++++++++++ riscv/run | 41 ++++++ riscv/sbi.c | 41 ++++++ riscv/selftest.c | 100 ++++++++++++++ riscv/sieve.c | 1 + riscv/unittests.cfg | 37 +++++ 63 files changed, 2616 insertions(+), 267 deletions(-) delete mode 100644 lib/arm64/asm/cpumask.h rename lib/{arm/asm => }/cpumask.h (72%) create mode 100644 lib/memregions.c create mode 100644 lib/memregions.h create mode 100644 lib/on-cpus.c create mode 100644 lib/on-cpus.h create mode 100644 lib/riscv/.gitignore create mode 100644 lib/riscv/asm-offsets.c create mode 100644 lib/riscv/asm/asm-offsets.h create mode 100644 lib/riscv/asm/barrier.h create mode 100644 lib/riscv/asm/bitops.h create mode 100644 lib/riscv/asm/bug.h create mode 100644 lib/riscv/asm/csr.h create mode 100644 lib/riscv/asm/io.h create mode 100644 lib/riscv/asm/isa.h create mode 100644 lib/riscv/asm/memory_areas.h create mode 100644 lib/riscv/asm/mmu.h create mode 100644 lib/riscv/asm/page.h create mode 100644 lib/riscv/asm/pgtable.h create mode 100644 lib/riscv/asm/processor.h create mode 100644 lib/riscv/asm/ptrace.h create mode 100644 lib/riscv/asm/sbi.h create mode 100644 lib/riscv/asm/setup.h create mode 100644 lib/riscv/asm/smp.h create mode 100644 lib/riscv/asm/spinlock.h create mode 100644 lib/riscv/asm/stack.h create mode 100644 lib/riscv/bitops.c create mode 100644 lib/riscv/io.c create mode 100644 lib/riscv/isa.c create mode 100644 lib/riscv/mmu.c create mode 100644 lib/riscv/processor.c create mode 100644 lib/riscv/sbi.c create mode 100644 lib/riscv/setup.c create mode 100644 lib/riscv/smp.c create mode 100644 lib/riscv/stack.c create mode 100644 riscv/Makefile create mode 100644 riscv/cstart.S create mode 100644 riscv/flat.lds create mode 100755 riscv/run create mode 100644 riscv/sbi.c create mode 100644 riscv/selftest.c create mode 120000 riscv/sieve.c create mode 100644 riscv/unittests.cfg