| Message ID | 20260925-jk-e825c-timestamp-processing-logic-fixes-srcu-v3-13-6532598e8da8@intel.com |
|---|---|
| State | Under Review |
| Delegated to: | Anthony Nguyen |
| Headers | show |
| Series | ice: E82x: timestamp processing logic fixes | expand |
> -----Original Message----- > From: Jacob Keller <jacob.e.keller@intel.com> > Sent: Friday, September 25, 2026 4:57 PM > To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Machnikowski, Maciej <maciej.machnikowski@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>; Korba, Przemyslaw <przemyslaw.korba@intel.com>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; Nitka, Grzegorz <grzegorz.nitka@intel.com>; Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com> > Cc: Keller, Jacob E <jacob.e.keller@intel.com> > Subject: [PATCH iwl-net v3 13/15] ice: skip reading Tx ready bitmap on ports with no timestamps > > On E82x devices, the interrupt for Tx timestamps are handled by the clock owner. When an interrupt with the Tx timestamp cause is fired, the clock owner PF iterates the list of ports and checks for timestamps across all ports. > > The existing logic reads the PHY timestamp ready bitmap before iterating the list of in-use timestamp indexes, even for ports which have no timestamps waiting in the software timestamp tracker. This has a significant and measurable latency impact on reporting Tx timestamps. > > Check the bitmap and exit early in the event that there are no timestamps waiting on a port. Observant reviewers may notice that the check is done without acquiring the lock. This is fine, as whether the thread > sees or fails to see a new outstanding timestamp does not affect correctness, only determining whether or not it should do extra work. > > Skipping the check has the highest impact on E822 an E825 devices which iterate all ports in a single thread, but it is applied universally to all device types since the extra read is unnecessary regardless. > > The average latency of a Tx timestamp is impacted by several factors including system load, the number of timestamp requests, and some random factors that are difficult to control. However for comparison on > my system with these changes, while operating ptp4l on a single port with a sync rate of 16/second: > > Before: mean 317.43 microseconds, standard deviation 34.51 > After: mean 189.71 microseconds, standard deviation 43.24 > > Of course this level of improvement may not be indicative of a production setup as one might expect timestamps to be operating out of multiple ports on the device. However, even in that case an improvement is still likely depending on the actual timestamp rates. > > Fixes: d938a8cca88a ("ice: Auxbus devices & driver for E822 TS") > Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> > --- > drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Tested-by: Alexander Nowlin <alexander.nowlin@intel.com>
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index a5ee8c8edf3d..9dc0b5fa3319 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -576,7 +576,7 @@ static void ice_ptp_process_tx_tstamp(struct ice_ptp_tx *tx) pf = ptp_port_to_pf(ptp_port); hw = &pf->hw; - if (!tx->init) + if (!tx->init || bitmap_empty(tx->in_use, tx->len)) return; /* Read the Tx ready status first */
On E82x devices, the interrupt for Tx timestamps are handled by the clock owner. When an interrupt with the Tx timestamp cause is fired, the clock owner PF iterates the list of ports and checks for timestamps across all ports. The existing logic reads the PHY timestamp ready bitmap before iterating the list of in-use timestamp indexes, even for ports which have no timestamps waiting in the software timestamp tracker. This has a significant and measurable latency impact on reporting Tx timestamps. Check the bitmap and exit early in the event that there are no timestamps waiting on a port. Observant reviewers may notice that the check is done without acquiring the lock. This is fine, as whether the thread sees or fails to see a new outstanding timestamp does not affect correctness, only determining whether or not it should do extra work. Skipping the check has the highest impact on E822 an E825 devices which iterate all ports in a single thread, but it is applied universally to all device types since the extra read is unnecessary regardless. The average latency of a Tx timestamp is impacted by several factors including system load, the number of timestamp requests, and some random factors that are difficult to control. However for comparison on my system with these changes, while operating ptp4l on a single port with a sync rate of 16/second: Before: mean 317.43 microseconds, standard deviation 34.51 After: mean 189.71 microseconds, standard deviation 43.24 Of course this level of improvement may not be indicative of a production setup as one might expect timestamps to be operating out of multiple ports on the device. However, even in that case an improvement is still likely depending on the actual timestamp rates. Fixes: d938a8cca88a ("ice: Auxbus devices & driver for E822 TS") Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)