| Message ID | 20260925-jk-e825c-timestamp-processing-logic-fixes-srcu-v3-10-6532598e8da8@intel.com |
|---|---|
| State | Under Review |
| Delegated to: | Anthony Nguyen |
| Headers | show |
| Series | ice: E82x: timestamp processing logic fixes | expand |
> -----Original Message----- > From: Jacob Keller <jacob.e.keller@intel.com> > Sent: Saturday, September 26, 2026 1:57 AM > To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Machnikowski, > Maciej <maciej.machnikowski@intel.com>; Keller, Jacob E > <jacob.e.keller@intel.com>; Korba, Przemyslaw > <przemyslaw.korba@intel.com>; Nguyen, Anthony L > <anthony.l.nguyen@intel.com>; Nitka, Grzegorz > <grzegorz.nitka@intel.com>; Kubalewski, Arkadiusz > <arkadiusz.kubalewski@intel.com> > Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Machnikowski, Maciej > <maciej.machnikowski@intel.com> > Subject: [PATCH iwl-net v3 10/15] ice: E825: perform a soft reset when > starting the PHY timer > > To ensure that the E825 PHY timer begins in a clean state, initiate a > PHY soft reset prior to programming the PHY. This ensures that we > clear any outstanding Tx timestamp memory, and ensures that the PHY > internal state including its timestamp counter has been reset. > > Note that despite the name, this PHY soft reset only impacts the timer > block of the PHY, and not its regular Tx/Rx functionality. > Additionally, many configuration registers such as the > PHY_REG_TS_INT_CONFIG and PHY_REG_TX_OFFSET_READY are not reset. > > Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C > products") > Reviewed-by: Maciek Machnikowski <maciej.machnikowski@intel.com> > Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> > --- > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c > b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c > index e83ad2bb8d42..e5bfede90431 100644 > --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c > +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c > @@ -2128,9 +2128,11 @@ int ice_stop_phy_timer_eth56g(struct ice_hw > *hw, u8 port) > * @hw: pointer to the HW struct > * @port: the PHY port to start > * > - * Start the clock of a PHY port. This must be done as part of the > flow to > - * re-calibrate Tx and Rx timestamping offsets whenever the clock > time is > - * initialized or when link speed changes. > + * Perform a PHY soft reset and then start the clock for the PHY > port. > + * > + * This must be done as part of the flow to re-calibrate Tx and Rx > + * timestamping offsets whenever the clock time is initialized or > when > + link > + * speed changes. > * > * Return: > * * %0 - success > @@ -2150,6 +2152,10 @@ int ice_start_phy_timer_eth56g(struct ice_hw > *hw, u8 port) > if (err) > return err; > > + err = ice_ptp_phy_soft_reset_eth56g(hw, port); > + if (err) > + return err; > + > ice_ptp_src_cmd(hw, ICE_PTP_NOP); > > err = ice_phy_cfg_parpcs_eth56g(hw, port); > > -- > 2.56.0.rc0.395.gd1f3524e15dc Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
> -----Original Message----- > From: Jacob Keller <jacob.e.keller@intel.com> > Sent: Friday, September 25, 2026 4:57 PM > To: Intel Wired LAN <intel-wired-lan@lists.osuosl.org>; Machnikowski, Maciej <maciej.machnikowski@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>; Korba, Przemyslaw <przemyslaw.korba@intel.com>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; Nitka, Grzegorz <grzegorz.nitka@intel.com>; Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com> > Cc: Keller, Jacob E <jacob.e.keller@intel.com>; Machnikowski, Maciej <maciej.machnikowski@intel.com> > Subject: [PATCH iwl-net v3 10/15] ice: E825: perform a soft reset when starting the PHY timer > > To ensure that the E825 PHY timer begins in a clean state, initiate a PHY soft reset prior to programming the PHY. This ensures that we clear any outstanding Tx timestamp memory, and ensures that the PHY internal state including its timestamp counter has been reset. > > Note that despite the name, this PHY soft reset only impacts the timer block of the PHY, and not its regular Tx/Rx functionality. Additionally, many configuration registers such as the PHY_REG_TS_INT_CONFIG and PHY_REG_TX_OFFSET_READY are not reset. > > Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products") > Reviewed-by: Maciek Machnikowski <maciej.machnikowski@intel.com> > Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> > --- > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) Tested-by: Alexander Nowlin <alexander.nowlin@intel.com>
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index e83ad2bb8d42..e5bfede90431 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2128,9 +2128,11 @@ int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port) * @hw: pointer to the HW struct * @port: the PHY port to start * - * Start the clock of a PHY port. This must be done as part of the flow to - * re-calibrate Tx and Rx timestamping offsets whenever the clock time is - * initialized or when link speed changes. + * Perform a PHY soft reset and then start the clock for the PHY port. + * + * This must be done as part of the flow to re-calibrate Tx and Rx + * timestamping offsets whenever the clock time is initialized or when link + * speed changes. * * Return: * * %0 - success @@ -2150,6 +2152,10 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) if (err) return err; + err = ice_ptp_phy_soft_reset_eth56g(hw, port); + if (err) + return err; + ice_ptp_src_cmd(hw, ICE_PTP_NOP); err = ice_phy_cfg_parpcs_eth56g(hw, port);
To ensure that the E825 PHY timer begins in a clean state, initiate a PHY soft reset prior to programming the PHY. This ensures that we clear any outstanding Tx timestamp memory, and ensures that the PHY internal state including its timestamp counter has been reset. Note that despite the name, this PHY soft reset only impacts the timer block of the PHY, and not its regular Tx/Rx functionality. Additionally, many configuration registers such as the PHY_REG_TS_INT_CONFIG and PHY_REG_TX_OFFSET_READY are not reset. Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products") Reviewed-by: Maciek Machnikowski <maciej.machnikowski@intel.com> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)