| Message ID | 20250422160149.1131069-4-arkadiusz.kubalewski@intel.com |
|---|---|
| State | Under Review |
| Delegated to: | Anthony Nguyen |
| Headers | show |
| Series | ice: decouple control of SMA/U.FL/SDP pins | expand |
> -----Original Message----- > From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Arkadiusz Kubalewski > Sent: 22 April 2025 21:32 > To: intel-wired-lan@lists.osuosl.org > Cc: netdev@vger.kernel.org; Kolacinski, Karol <karol.kolacinski@intel.com>; Olech, Milena <milena.olech@intel.com>; Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com> > Subject: [Intel-wired-lan] [PATCH iwl-next v5 3/3] ice: add ice driver PTP pin documentation > > From: Karol Kolacinski <karol.kolacinski@intel.com> > > Add a description of PTP pins support by the adapters to ice driver documentation. > > Reviewed-by: Milena Olech <milena.olech@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> > --- > v5: > - no change. > --- > .../device_drivers/ethernet/intel/ice.rst | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
diff --git a/Documentation/networking/device_drivers/ethernet/intel/ice.rst b/Documentation/networking/device_drivers/ethernet/intel/ice.rst index 3c46a48d99ba..0bca293cf9cb 100644 --- a/Documentation/networking/device_drivers/ethernet/intel/ice.rst +++ b/Documentation/networking/device_drivers/ethernet/intel/ice.rst @@ -927,6 +927,19 @@ To enable/disable UDP Segmentation Offload, issue the following command:: # ethtool -K <ethX> tx-udp-segmentation [off|on] +PTP pin interface +----------------- +All adapters support standard PTP pin interface. SDPs (Software Definable Pin) +are single ended pins with both periodic output and external timestamp +supported. There are also specific differential input/output pins (TIME_SYNC, +1PPS) with only one of the functions supported. + +There are adapters with DPLL, where pins are connected to the DPLL instead of +being exposed on the board. You have to be aware that in those configurations, +only SDP pins are exposed and each pin has its own fixed direction. +To see input signal on those PTP pins, you need to configure DPLL properly. +Output signal is only visible on DPLL and to send it to the board SMA/U.FL pins, +DPLL output pins have to be manually configured. GNSS module -----------