[iwl-next,v2,09/15] ice: init XLT key builder for parser

diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c
index e8f047c08cd9..507b06f1fcfe 100644
--- a/drivers/net/ethernet/intel/ice/ice_parser.c
+++ b/drivers/net/ethernet/intel/ice/ice_parser.c
@@ -248,6 +248,30 @@  int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr)
 		goto err;
 	}
 
+	p->xlt_kb_sw = ice_xlt_kb_get_sw(hw);
+	if (!p->xlt_kb_sw) {
+		status = -EINVAL;
+		goto err;
+	}
+
+	p->xlt_kb_acl = ice_xlt_kb_get_acl(hw);
+	if (!p->xlt_kb_acl) {
+		status = -EINVAL;
+		goto err;
+	}
+
+	p->xlt_kb_fd = ice_xlt_kb_get_fd(hw);
+	if (!p->xlt_kb_fd) {
+		status = -EINVAL;
+		goto err;
+	}
+
+	p->xlt_kb_rss = ice_xlt_kb_get_rss(hw);
+	if (!p->xlt_kb_rss) {
+		status = -EINVAL;
+		goto err;
+	}
+
 	*psr = p;
 	return 0;
 err:
@@ -273,6 +297,10 @@  void ice_parser_destroy(struct ice_parser *psr)
 	devm_kfree(ice_hw_to_dev(psr->hw), psr->mk_grp_table);
 	devm_kfree(ice_hw_to_dev(psr->hw), psr->proto_grp_table);
 	devm_kfree(ice_hw_to_dev(psr->hw), psr->flg_rd_table);
+	devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_sw);
+	devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_acl);
+	devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_fd);
+	devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_rss);
 
 	devm_kfree(ice_hw_to_dev(psr->hw), psr);
 }
diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h
index 5eed54d9d189..8222e738d493 100644
--- a/drivers/net/ethernet/intel/ice/ice_parser.h
+++ b/drivers/net/ethernet/intel/ice/ice_parser.h
@@ -12,6 +12,7 @@ 
 #include "ice_mk_grp.h"
 #include "ice_proto_grp.h"
 #include "ice_flg_rd.h"
+#include "ice_xlt_kb.h"
 
 struct ice_parser {
 	struct ice_hw *hw; /* pointer to the hardware structure */
@@ -40,6 +41,14 @@  struct ice_parser {
 	struct ice_proto_grp_item *proto_grp_table;
 	/* load data from section ICE_SID_RXPARSER_FLAG_REDIR */
 	struct ice_flg_rd_item *flg_rd_table;
+	/* load data from section ICE_SID_XLT_KEY_BUILDER_SW */
+	struct ice_xlt_kb *xlt_kb_sw;
+	/* load data from section ICE_SID_XLT_KEY_BUILDER_ACL */
+	struct ice_xlt_kb *xlt_kb_acl;
+	/* load data from section ICE_SID_XLT_KEY_BUILDER_FD */
+	struct ice_xlt_kb *xlt_kb_fd;
+	/* load data from section ICE_SID_XLT_KEY_BUILDER_RSS */
+	struct ice_xlt_kb *xlt_kb_rss;
 };
 
 int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr);
diff --git a/drivers/net/ethernet/intel/ice/ice_xlt_kb.c b/drivers/net/ethernet/intel/ice/ice_xlt_kb.c
new file mode 100644
index 000000000000..146602dd6b57
--- /dev/null
+++ b/drivers/net/ethernet/intel/ice/ice_xlt_kb.c
@@ -0,0 +1,191 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2018-2023 Intel Corporation */
+
+#include "ice_common.h"
+
+#define ICE_XLT_KB_TBL_OFF 12
+#define ICE_XLT_KB_TBL_ENTRY_SIZE 24
+
+static void _xlt_kb_entry_dump(struct ice_hw *hw,
+			       struct ice_xlt_kb_entry *entry, int idx)
+{
+	int i;
+
+	dev_info(ice_hw_to_dev(hw), "key builder entry %d\n", idx);
+	dev_info(ice_hw_to_dev(hw), "\txlt1_ad_sel = %d\n",
+		 entry->xlt1_ad_sel);
+	dev_info(ice_hw_to_dev(hw), "\txlt2_ad_sel = %d\n",
+		 entry->xlt2_ad_sel);
+
+	for (i = 0; i < ICE_XLT_KB_FLAG0_14_CNT; i++)
+		dev_info(ice_hw_to_dev(hw), "\tflg%d_sel = %d\n", i,
+			 entry->flg0_14_sel[i]);
+
+	dev_info(ice_hw_to_dev(hw), "\txlt1_md_sel = %d\n",
+		 entry->xlt1_md_sel);
+	dev_info(ice_hw_to_dev(hw), "\txlt2_md_sel = %d\n",
+		 entry->xlt2_md_sel);
+}
+
+/**
+ * ice_xlt_kb_dump - dump a xlt key build info
+ * @hw: pointer to the hardware structure
+ * @kb: key build to dump
+ */
+void ice_xlt_kb_dump(struct ice_hw *hw, struct ice_xlt_kb *kb)
+{
+	int i;
+
+	dev_info(ice_hw_to_dev(hw), "xlt1_pm = %d\n", kb->xlt1_pm);
+	dev_info(ice_hw_to_dev(hw), "xlt2_pm = %d\n", kb->xlt2_pm);
+	dev_info(ice_hw_to_dev(hw), "prof_id_pm = %d\n", kb->prof_id_pm);
+	dev_info(ice_hw_to_dev(hw), "flag15 low  = 0x%08x\n", (u32)kb->flag15);
+	dev_info(ice_hw_to_dev(hw), "flag15 high = 0x%08x\n",
+		 (u32)(kb->flag15 >> 32));
+
+	for (i = 0; i < ICE_XLT_KB_TBL_CNT; i++)
+		_xlt_kb_entry_dump(hw, &kb->entries[i], i);
+}
+
+/** The function parses a 192 bits XLT Key Build entry with below format:
+ *  BIT 0-31:	reserved
+ *  BIT 32-34:	XLT1 AdSel (entry->xlt1_ad_sel)
+ *  BIT 35-37:	XLT2 AdSel (entry->xlt2_ad_sel)
+ *  BIT 38-46:	Flag 0 Select (entry->flg0_14_sel[0])
+ *  BIT 47-55:	Flag 1 Select (entry->flg0_14_sel[1])
+ *  BIT 56-64:	Flag 2 Select (entry->flg0_14_sel[2])
+ *  BIT 65-73:	Flag 3 Select (entry->flg0_14_sel[3])
+ *  BIT 74-82:	Flag 4 Select (entry->flg0_14_sel[4])
+ *  BIT 83-91:	Flag 5 Select (entry->flg0_14_sel[5])
+ *  BIT 92-100:	Flag 6 Select (entry->flg0_14_sel[6])
+ *  BIT 101-109:Flag 7 Select (entry->flg0_14_sel[7])
+ *  BIT 110-118:Flag 8 Select (entry->flg0_14_sel[8])
+ *  BIT 119-127:Flag 9 Select (entry->flg0_14_sel[9])
+ *  BIT 128-136:Flag 10 Select (entry->flg0_14_sel[10])
+ *  BIT 137-145:Flag 11 Select (entry->flg0_14_sel[11])
+ *  BIT 146-154:Flag 12 Select (entry->flg0_14_sel[12])
+ *  BIT 155-163:Flag 13 Select (entry->flg0_14_sel[13])
+ *  BIT 164-172:Flag 14 Select (entry->flg0_14_sel[14])
+ *  BIT 173-181:reserved
+ *  BIT 182-186:XLT1 MdSel (entry->xlt1_md_sel)
+ *  BIT 187-191:XLT2 MdSel (entry->xlt2_md_sel)
+ */
+static void _kb_entry_init(struct ice_xlt_kb_entry *entry, u8 *data)
+{
+	u64 d64 = *(u64 *)&data[4];
+
+	entry->xlt1_ad_sel = (u8)(d64 & 0x7);
+	entry->xlt2_ad_sel = (u8)((d64 >> 3) & 0x7);
+	entry->flg0_14_sel[0] = (u16)((d64 >> 6) & 0x1ff);
+	entry->flg0_14_sel[1] = (u16)((d64 >> 15) & 0x1ff);
+	entry->flg0_14_sel[2] = (u16)((d64 >> 24) & 0x1ff);
+	entry->flg0_14_sel[3] = (u16)((d64 >> 33) & 0x1ff);
+	entry->flg0_14_sel[4] = (u16)((d64 >> 42) & 0x1ff);
+	entry->flg0_14_sel[5] = (u16)((d64 >> 51) & 0x1ff);
+
+	d64 = (*(u64 *)&data[11] >> 4);
+	entry->flg0_14_sel[6] = (u16)(d64 & 0x1ff);
+	entry->flg0_14_sel[7] = (u16)((d64 >> 9) & 0x1ff);
+	entry->flg0_14_sel[8] = (u16)((d64 >> 18) & 0x1ff);
+	entry->flg0_14_sel[9] = (u16)((d64 >> 27) & 0x1ff);
+	entry->flg0_14_sel[10] = (u16)((d64 >> 36) & 0x1ff);
+	entry->flg0_14_sel[11] = (u16)((d64 >> 45) & 0x1ff);
+
+	d64 = (*(u64 *)&data[18] >> 2);
+	entry->flg0_14_sel[12] = (u16)(d64 & 0x1ff);
+	entry->flg0_14_sel[13] = (u16)((d64 >> 9) & 0x1ff);
+	entry->flg0_14_sel[14] = (u16)((d64 >> 18) & 0x1ff);
+
+	entry->xlt1_md_sel = (u8)((d64 >> 36) & 0x1f);
+	entry->xlt2_md_sel = (u8)((d64 >> 41) & 0x1f);
+}
+
+/** The function parses a 204 bytes XLT Key Build Table with below format:
+ *  byte 0:	XLT1 Partition Mode (kb->xlt1_pm)
+ *  byte 1:	XLT2 Partition Mode (kb->xlt2_pm)
+ *  byte 2:	Profile ID Partition Mode (kb->prof_id_pm)
+ *  byte 3:	reserved
+ *  byte 4-11:	Flag15 Mask (kb->flag15)
+ *  byte 12-203:8 Key Build entries (kb->entries)
+ */
+static void _parse_kb_data(struct ice_hw *hw, struct ice_xlt_kb *kb, void *data)
+{
+	u8 *buf = data;
+	int i;
+
+	kb->xlt1_pm = buf[0];
+	kb->xlt2_pm = buf[1];
+	kb->prof_id_pm = buf[2];
+
+	kb->flag15 = *(u64 *)&buf[4];
+	for (i = 0; i < ICE_XLT_KB_TBL_CNT; i++)
+		_kb_entry_init(&kb->entries[i],
+			       &buf[ICE_XLT_KB_TBL_OFF +
+				    i * ICE_XLT_KB_TBL_ENTRY_SIZE]);
+
+	if (hw->debug_mask & ICE_DBG_PARSER)
+		ice_xlt_kb_dump(hw, kb);
+}
+
+static struct ice_xlt_kb *_xlt_kb_get(struct ice_hw *hw, u32 sect_type)
+{
+	struct ice_seg *seg = hw->seg;
+	struct ice_pkg_enum state;
+	struct ice_xlt_kb *kb;
+	void *data;
+
+	if (!seg)
+		return NULL;
+
+	kb = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*kb), GFP_KERNEL);
+	if (!kb)
+		return NULL;
+
+	memset(&state, 0, sizeof(state));
+	data = ice_pkg_enum_section(seg, &state, sect_type);
+	if (!data) {
+		ice_debug(hw, ICE_DBG_PARSER, "failed to find section type %d.\n",
+			  sect_type);
+		return NULL;
+	}
+
+	_parse_kb_data(hw, kb, data);
+
+	return kb;
+}
+
+/**
+ * ice_xlt_kb_get_sw - create switch xlt key build
+ * @hw: pointer to the hardware structure
+ */
+struct ice_xlt_kb *ice_xlt_kb_get_sw(struct ice_hw *hw)
+{
+	return _xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_SW);
+}
+
+/**
+ * ice_xlt_kb_get_acl - create acl xlt key build
+ * @hw: pointer to the hardware structure
+ */
+struct ice_xlt_kb *ice_xlt_kb_get_acl(struct ice_hw *hw)
+{
+	return _xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_ACL);
+}
+
+/**
+ * ice_xlt_kb_get_fd - create fdir xlt key build
+ * @hw: pointer to the hardware structure
+ */
+struct ice_xlt_kb *ice_xlt_kb_get_fd(struct ice_hw *hw)
+{
+	return _xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_FD);
+}
+
+/**
+ * ice_xlt_kb_get_rss - create rss xlt key build
+ * @hw: pointer to the hardware structure
+ */
+struct ice_xlt_kb *ice_xlt_kb_get_rss(struct ice_hw *hw)
+{
+	return _xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_RSS);
+}
diff --git a/drivers/net/ethernet/intel/ice/ice_xlt_kb.h b/drivers/net/ethernet/intel/ice/ice_xlt_kb.h
new file mode 100644
index 000000000000..f15c3d8f3695
--- /dev/null
+++ b/drivers/net/ethernet/intel/ice/ice_xlt_kb.h
@@ -0,0 +1,32 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2018-2023 Intel Corporation */
+
+#ifndef _ICE_XLT_KB_H_
+#define _ICE_XLT_KB_H_
+
+#define ICE_XLT_KB_TBL_CNT 8
+#define ICE_XLT_KB_FLAG0_14_CNT 15
+
+struct ice_xlt_kb_entry {
+	u8 xlt1_ad_sel;
+	u8 xlt2_ad_sel;
+	u16 flg0_14_sel[ICE_XLT_KB_FLAG0_14_CNT];
+	u8 xlt1_md_sel;
+	u8 xlt2_md_sel;
+};
+
+struct ice_xlt_kb {
+	u8 xlt1_pm;
+	u8 xlt2_pm;
+	u8 prof_id_pm;
+	u64 flag15;
+
+	struct ice_xlt_kb_entry entries[ICE_XLT_KB_TBL_CNT];
+};
+
+void ice_xlt_kb_dump(struct ice_hw *hw, struct ice_xlt_kb *kb);
+struct ice_xlt_kb *ice_xlt_kb_get_sw(struct ice_hw *hw);
+struct ice_xlt_kb *ice_xlt_kb_get_acl(struct ice_hw *hw);
+struct ice_xlt_kb *ice_xlt_kb_get_fd(struct ice_hw *hw);
+struct ice_xlt_kb *ice_xlt_kb_get_rss(struct ice_hw *hw);
+#endif /* _ICE_XLT_KB_H */