diff mbox series

[net-next,v1] igc: Fix qbv counter not zero during 1st GCL enrollment

Message ID 20230208054517.5615-1-muhammad.husaini.zulkifli@intel.com
State Changes Requested
Headers show
Series [net-next,v1] igc: Fix qbv counter not zero during 1st GCL enrollment | expand

Commit Message

Zulkifli, Muhammad Husaini Feb. 8, 2023, 5:45 a.m. UTC
The counter is experiencing some problems as a result of recent updates
that prevent the controller from being reset each time the TSN config
is disabled because the BASET L/H value will always be increased rather
than zero. Previous condition is no longer valid anymore.

The TQAVCTRL[bit0] register is used in this patch to check whether the
existing GCL is being reconfigured or a new GCL configuration.

Fixes: 1d1b4c63ba73 ("igc: Remove reset adapter task for i226 during disable tsn config")
Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
---
 drivers/net/ethernet/intel/igc/igc_tsn.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Tony Nguyen Feb. 15, 2023, 7:09 p.m. UTC | #1
On 2/7/2023 9:45 PM, Muhammad Husaini Zulkifli wrote:
> The counter is experiencing some problems as a result of recent updates
> that prevent the controller from being reset each time the TSN config
> is disabled because the BASET L/H value will always be increased rather
> than zero. Previous condition is no longer valid anymore.
> 
> The TQAVCTRL[bit0] register is used in this patch to check whether the
> existing GCL is being reconfigured or a new GCL configuration.

Since the qbv counters patch [1] is not accepted yet, please squash this 
patch into that. I've dropped that patch from the tree so you can update.

Thanks,
Tony

> Fixes: 1d1b4c63ba73 ("igc: Remove reset adapter task for i226 during disable tsn config")
> Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>

[1] 
https://lore.kernel.org/intel-wired-lan/20230208054517.5615-1-muhammad.husaini.zulkifli@intel.com/
Zulkifli, Muhammad Husaini Feb. 15, 2023, 11:42 p.m. UTC | #2
Hi,

> -----Original Message-----
> From: Nguyen, Anthony L <anthony.l.nguyen@intel.com>
> Sent: Thursday, 16 February, 2023 3:10 AM
> To: Zulkifli, Muhammad Husaini <muhammad.husaini.zulkifli@intel.com>;
> intel-wired-lan@osuosl.org; Gomes, Vinicius <vinicius.gomes@intel.com>
> Cc: Neftin, Sasha <sasha.neftin@intel.com>; naamax.meir@linux.intel.com
> Subject: Re: [PATCH net-next v1] igc: Fix qbv counter not zero during 1st GCL
> enrollment
> 
> 
> 
> On 2/7/2023 9:45 PM, Muhammad Husaini Zulkifli wrote:
> > The counter is experiencing some problems as a result of recent
> > updates that prevent the controller from being reset each time the TSN
> > config is disabled because the BASET L/H value will always be
> > increased rather than zero. Previous condition is no longer valid anymore.
> >
> > The TQAVCTRL[bit0] register is used in this patch to check whether the
> > existing GCL is being reconfigured or a new GCL configuration.
> 
> Since the qbv counters patch [1] is not accepted yet, please squash this
> patch into that. I've dropped that patch from the tree so you can update.

Thanks. Will do.

> 
> Thanks,
> Tony
> 
> > Fixes: 1d1b4c63ba73 ("igc: Remove reset adapter task for i226 during
> > disable tsn config")
> > Signed-off-by: Muhammad Husaini Zulkifli
> > <muhammad.husaini.zulkifli@intel.com>
> 
> [1]
> https://lore.kernel.org/intel-wired-lan/20230208054517.5615-1-
> muhammad.husaini.zulkifli@intel.com/
diff mbox series

Patch

diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/ethernet/intel/igc/igc_tsn.c
index b38c1c7569a0b..94a2b0dfb54d4 100644
--- a/drivers/net/ethernet/intel/igc/igc_tsn.c
+++ b/drivers/net/ethernet/intel/igc/igc_tsn.c
@@ -114,6 +114,7 @@  static int igc_tsn_disable_offload(struct igc_adapter *adapter)
 static int igc_tsn_enable_offload(struct igc_adapter *adapter)
 {
 	struct igc_hw *hw = &adapter->hw;
+	bool tsn_mode_reconfig = false;
 	u32 tqavctrl, baset_l, baset_h;
 	u32 sec, nsec, cycle;
 	ktime_t base_time, systim;
@@ -226,6 +227,10 @@  static int igc_tsn_enable_offload(struct igc_adapter *adapter)
 	}
 
 	tqavctrl = rd32(IGC_TQAVCTRL) & ~IGC_TQAVCTRL_FUTSCDDIS;
+
+	if (tqavctrl & IGC_TQAVCTRL_TRANSMIT_MODE_TSN)
+		tsn_mode_reconfig = true;
+
 	tqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV;
 
 	cycle = adapter->cycle_time;
@@ -243,7 +248,8 @@  static int igc_tsn_enable_offload(struct igc_adapter *adapter)
 		/* Increase the counter if scheduling into the past while
 		 * Gate Control List (GCL) is running.
 		 */
-		if (rd32(IGC_BASET_H) || rd32(IGC_BASET_L))
+		if ((rd32(IGC_BASET_H) || rd32(IGC_BASET_L)) &&
+		    tsn_mode_reconfig)
 			adapter->qbv_config_change_errors++;
 	} else {
 		/* According to datasheet section 7.5.2.9.3.3, FutScdDis bit