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Thu, 21 Jul 2022 21:30:10 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6400,9594,10415"; a="274029232" X-IronPort-AV: E=Sophos;i="5.93,183,1654585200"; d="scan'208";a="274029232" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2022 14:30:09 -0700 X-IronPort-AV: E=Sophos;i="5.93,183,1654585200"; d="scan'208";a="740833151" Received: from jekeller-desk.amr.corp.intel.com ([10.166.241.7]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2022 14:30:09 -0700 From: Jacob Keller To: Intel Wired LAN Date: Thu, 21 Jul 2022 14:29:58 -0700 Message-Id: <20220721213001.2483596-6-jacob.e.keller@intel.com> X-Mailer: git-send-email 2.35.1.456.ga9c7032d4631 In-Reply-To: <20220721213001.2483596-1-jacob.e.keller@intel.com> References: <20220721213001.2483596-1-jacob.e.keller@intel.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658439010; x=1689975010; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VUqh+1jVWKo0nPQcxnFra4hX/tjkm993rkXEKiDkcTU=; b=Oi74P/YluJhi3sPYgDuaaJKw4l912kSYguiB0Bglr8LDSfy3oOCOfwqs SxzjIKIBtrPgNbrD634m8BWnqYkdV5sO7wwubhyafM7HswtPGQ1F5MEYN 7CQOQL9ONJwcdLIzAwKPPHRTHIaJGJRnCPsAb0KffEvuKJMK4K6SEC3Ji YRgac6z2Izvb+M00gD3mqCjIfkiEVUHxwlnYxlPJPetIAN32OAonwo8Bl blOA+pg6lESUs5XrQatHzqi6VgCh8PHrs5ANjrvhbtF8M7aiZ/UxoIzku teHd0pSM8wXVfJPv4r+/U0lgV61wWFPwymjutYJ0jkiNI/Ymab5vP7z2v Q==; X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Oi74P/Yl Subject: [Intel-wired-lan] [net-next PATCH 4/7] i40e: use mul_u64_u64_div_u64 for PTP frequency calculation X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" The i40e device has a different clock rate depending on the current link speed. This requires using a different increment rate for the PTP clock registers. For slower link speeds, the base increment value is larger. Directly multiplying the larger increment value by the parts per billion adjustment might overflow. To avoid this, the i40e implementation defaults to using the lower increment value and then multiplying the adjustment afterwards. This causes a loss of precision for lower link speeds. We can fix this by using mul_u64_u64_div_u64 instead of performing the multiplications using standard C operations. On X86, this will use special instructions that perform the multiplication and division with 128bit intermediate values. For other architectures, the fallback implementation will limit the loss of precision for large values. Small adjustments don't overflow anyways and won't lose precision at all. This allows first multiplying the base increment value and then performing the adjustment calculation, since we no longer fear overflowing. It also makes it easier to convert to the even more precise .adjfine implementation in a following change. Signed-off-by: Jacob Keller Tested-by: Gurucharan (A Contingent worker at Intel) --- drivers/net/ethernet/intel/i40e/i40e_ptp.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_ptp.c b/drivers/net/ethernet/intel/i40e/i40e_ptp.c index 57a71fa17ed5..15de918abc41 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_ptp.c +++ b/drivers/net/ethernet/intel/i40e/i40e_ptp.c @@ -353,25 +353,16 @@ static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) ppb = -ppb; } - freq = I40E_PTP_40GB_INCVAL; - freq *= ppb; - diff = div_u64(freq, 1000000000ULL); + smp_mb(); /* Force any pending update before accessing. */ + freq = I40E_PTP_40GB_INCVAL * READ_ONCE(pf->ptp_adj_mult); + diff = mul_u64_u64_div_u64(freq, (u64)ppb, + 1000000000ULL); if (neg_adj) adj = I40E_PTP_40GB_INCVAL - diff; else adj = I40E_PTP_40GB_INCVAL + diff; - /* At some link speeds, the base incval is so large that directly - * multiplying by ppb would result in arithmetic overflow even when - * using a u64. Avoid this by instead calculating the new incval - * always in terms of the 40GbE clock rate and then multiplying by the - * link speed factor afterwards. This does result in slightly lower - * precision at lower link speeds, but it is fairly minor. - */ - smp_mb(); /* Force any pending update before accessing. */ - adj *= READ_ONCE(pf->ptp_adj_mult); - wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);