From patchwork Fri Dec 29 13:49:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael, Alice" X-Patchwork-Id: 854005 X-Patchwork-Delegate: jeffrey.t.kirsher@intel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=osuosl.org (client-ip=140.211.166.138; helo=whitealder.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org; receiver=) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3z7gRD19Zhz9s7G for ; Sat, 30 Dec 2017 08:56:56 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id A264684941; Fri, 29 Dec 2017 21:56:54 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id i3Brr5049t0R; Fri, 29 Dec 2017 21:56:53 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by whitealder.osuosl.org (Postfix) with ESMTP id 302008065F; Fri, 29 Dec 2017 21:56:53 +0000 (UTC) X-Original-To: intel-wired-lan@lists.osuosl.org Delivered-To: intel-wired-lan@lists.osuosl.org Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 84E331C0180 for ; Fri, 29 Dec 2017 21:56:51 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 80585878E6 for ; Fri, 29 Dec 2017 21:56:51 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Y+XhkdqRewVo for ; Fri, 29 Dec 2017 21:56:50 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by whitealder.osuosl.org (Postfix) with ESMTPS id 7C05E878DB for ; Fri, 29 Dec 2017 21:56:50 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Dec 2017 13:56:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,478,1508828400"; d="scan'208";a="6368080" Received: from alicemic-2.jf.intel.com ([10.166.16.121]) by orsmga007.jf.intel.com with ESMTP; 29 Dec 2017 13:56:49 -0800 From: Alice Michael To: alice.michael@intel.com, intel-wired-lan@lists.osuosl.org Date: Fri, 29 Dec 2017 08:49:53 -0500 Message-Id: <20171229134953.14355-1-alice.michael@intel.com> X-Mailer: git-send-email 2.9.5 Subject: [Intel-wired-lan] [next PATCH S85-V1 05/14] i40e/i40evf: Clean up logic for adaptive ITR X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" From: Alexander Duyck The logic for dynamic ITR update is confusing at best as there were odd paths chosen for how to find the rings associated with a given queue based on the vector index and other inconsistencies throughout the code. This patch is an attempt to clean up the logic so that we can more easily understand what is going on. Specifically if there is a Rx or Tx ring that is enabled in dynamic mode on the q_vector it is allowed to override the other side of the interrupt moderation. While it isn't correct all this patch is doing is cleaning up the logic for now so that when we come through and fix it we can more easily identify that this is wrong. The other big change made here is that we replace references to: vsi->rx_rings[q_vector->v_idx]->itr_setting with: q_vector->rx.ring->itr_setting The general idea is we can avoid the long pointer chase since just accessing q_vector->rx.ring is a single pointer access versus having to chase down vsi->rx_rings, and then finding the pointer in the array, and finally chasing down the itr_setting from there. Signed-off-by: Alexander Duyck Tested-by: Andrew Bowers --- drivers/net/ethernet/intel/i40e/i40e_txrx.c | 55 +++++++------------------ drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 59 +++++++-------------------- 2 files changed, 28 insertions(+), 86 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c index 44d360e..4e661ef 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c @@ -1015,6 +1015,9 @@ static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) int bytes_per_usec; unsigned int usecs, estimated_usecs; + if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting)) + return false; + if (rc->total_packets == 0 || !rc->itr) return false; @@ -2274,15 +2277,6 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr) /* a small macro to shorten up some long lines */ #define INTREG I40E_PFINT_DYN_CTLN -static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) -{ - return vsi->rx_rings[idx]->itr_setting; -} - -static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) -{ - return vsi->tx_rings[idx]->itr_setting; -} /** * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt @@ -2295,9 +2289,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, { struct i40e_hw *hw = &vsi->back->hw; bool rx = false, tx = false; - u32 rxval, txval; - int idx = q_vector->v_idx; - int rx_itr_setting, tx_itr_setting; + u32 txval; /* If we don't have MSIX, then we only need to re-enable icr0 */ if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) { @@ -2305,29 +2297,15 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, return; } - /* avoid dynamic calculation if in countdown mode OR if - * all dynamic is disabled - */ txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); - rx_itr_setting = get_rx_itr(vsi, idx); - tx_itr_setting = get_tx_itr(vsi, idx); - - if (q_vector->itr_countdown > 0 || - (!ITR_IS_DYNAMIC(rx_itr_setting) && - !ITR_IS_DYNAMIC(tx_itr_setting))) { + /* avoid dynamic calculation if in countdown mode */ + if (q_vector->itr_countdown > 0) goto enable_int; - } - if (ITR_IS_DYNAMIC(rx_itr_setting)) { - rx = i40e_set_new_dynamic_itr(&q_vector->rx); - rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); - } - - if (ITR_IS_DYNAMIC(tx_itr_setting)) { - tx = i40e_set_new_dynamic_itr(&q_vector->tx); - txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); - } + /* these will return false if dynamic mode is disabled */ + rx = i40e_set_new_dynamic_itr(&q_vector->rx); + tx = i40e_set_new_dynamic_itr(&q_vector->tx); if (rx || tx) { /* get the higher of the two ITR adjustments and @@ -2335,25 +2313,20 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, * when in adaptive mode (Rx and/or Tx) */ u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); + u32 rxval; q_vector->tx.itr = q_vector->rx.itr = itr; - txval = i40e_buildreg_itr(I40E_TX_ITR, itr); - tx = true; - rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); - rx = true; - } - /* only need to enable the interrupt once, but need - * to possibly update both ITR values - */ - if (rx) { /* set the INTENA_MSK_MASK so that this first write * won't actually enable the interrupt, instead just * updating the ITR (it's bit 31 PF and VF) */ - rxval |= BIT(31); + rxval = i40e_buildreg_itr(I40E_RX_ITR, itr) | BIT(31); + /* don't check _DOWN because interrupt isn't being enabled */ wr32(hw, INTREG(q_vector->reg_idx), rxval); + + txval = i40e_buildreg_itr(I40E_TX_ITR, itr); } enable_int: diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c index 291130a..3fd7e97 100644 --- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c @@ -413,6 +413,9 @@ static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) int bytes_per_usec; unsigned int usecs, estimated_usecs; + if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting)) + return false; + if (rc->total_packets == 0 || !rc->itr) return false; @@ -1471,19 +1474,6 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr) /* a small macro to shorten up some long lines */ #define INTREG I40E_VFINT_DYN_CTLN1 -static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) -{ - struct i40evf_adapter *adapter = vsi->back; - - return adapter->rx_rings[idx].itr_setting; -} - -static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) -{ - struct i40evf_adapter *adapter = vsi->back; - - return adapter->tx_rings[idx].itr_setting; -} /** * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt @@ -1496,33 +1486,17 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, { struct i40e_hw *hw = &vsi->back->hw; bool rx = false, tx = false; - u32 rxval, txval; - int idx = q_vector->v_idx; - int rx_itr_setting, tx_itr_setting; + u32 txval; - /* avoid dynamic calculation if in countdown mode OR if - * all dynamic is disabled - */ txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); - rx_itr_setting = get_rx_itr(vsi, idx); - tx_itr_setting = get_tx_itr(vsi, idx); - - if (q_vector->itr_countdown > 0 || - (!ITR_IS_DYNAMIC(rx_itr_setting) && - !ITR_IS_DYNAMIC(tx_itr_setting))) { + /* avoid dynamic calculation if in countdown mode */ + if (q_vector->itr_countdown > 0) goto enable_int; - } - if (ITR_IS_DYNAMIC(rx_itr_setting)) { - rx = i40e_set_new_dynamic_itr(&q_vector->rx); - rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); - } - - if (ITR_IS_DYNAMIC(tx_itr_setting)) { - tx = i40e_set_new_dynamic_itr(&q_vector->tx); - txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); - } + /* these will return false if dynamic mode is disabled */ + rx = i40e_set_new_dynamic_itr(&q_vector->rx); + tx = i40e_set_new_dynamic_itr(&q_vector->tx); if (rx || tx) { /* get the higher of the two ITR adjustments and @@ -1530,25 +1504,20 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, * when in adaptive mode (Rx and/or Tx) */ u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); + u32 rxval; q_vector->tx.itr = q_vector->rx.itr = itr; - txval = i40e_buildreg_itr(I40E_TX_ITR, itr); - tx = true; - rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); - rx = true; - } - /* only need to enable the interrupt once, but need - * to possibly update both ITR values - */ - if (rx) { /* set the INTENA_MSK_MASK so that this first write * won't actually enable the interrupt, instead just * updating the ITR (it's bit 31 PF and VF) */ - rxval |= BIT(31); + rxval = i40e_buildreg_itr(I40E_RX_ITR, itr) | BIT(31); + /* don't check _DOWN because interrupt isn't being enabled */ wr32(hw, INTREG(q_vector->reg_idx), rxval); + + txval = i40e_buildreg_itr(I40E_TX_ITR, itr); } enable_int: