| Message ID | 20230405162144.984598-4-hjl.tools@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | <sys/platform/x86.h>: Update CPUID features | expand |
On Wed, Apr 5, 2023 at 11:22 AM H.J. Lu via Libc-alpha <libc-alpha@sourceware.org> wrote: > > Add 57-bit linear addresses and five-level paging (LA57) support to > <sys/platform/x86.h>. > --- > manual/platform.texi | 3 +++ > sysdeps/x86/bits/platform/x86.h | 2 +- > sysdeps/x86/tst-get-cpu-features.c | 1 + > 3 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/manual/platform.texi b/manual/platform.texi > index c1cef570d2..9251b63e47 100644 > --- a/manual/platform.texi > +++ b/manual/platform.texi > @@ -394,6 +394,9 @@ the indirect branch predictor barrier (IBPB). > @item > @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR. > > +@item > +@code{LA57} -- 57-bit linear addresses and five-level paging. > + > @item > @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode. > > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h > index 1ed24d7024..c9189fa248 100644 > --- a/sysdeps/x86/bits/platform/x86.h > +++ b/sysdeps/x86/bits/platform/x86.h > @@ -182,7 +182,7 @@ enum > x86_cpu_INDEX_7_ECX_13 = x86_cpu_index_7_ecx + 13, > x86_cpu_AVX512_VPOPCNTDQ = x86_cpu_index_7_ecx + 14, > x86_cpu_INDEX_7_ECX_15 = x86_cpu_index_7_ecx + 15, > - x86_cpu_INDEX_7_ECX_16 = x86_cpu_index_7_ecx + 16, > + x86_cpu_LA57 = x86_cpu_index_7_ecx + 16, > /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX > instructions in 64-bit mode. */ > x86_cpu_RDPID = x86_cpu_index_7_ecx + 22, > diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c > index 1954698df8..5f5cd3e448 100644 > --- a/sysdeps/x86/tst-get-cpu-features.c > +++ b/sysdeps/x86/tst-get-cpu-features.c > @@ -144,6 +144,7 @@ do_test (void) > CHECK_CPU_FEATURE_PRESENT (AVX512_VNNI); > CHECK_CPU_FEATURE_PRESENT (AVX512_BITALG); > CHECK_CPU_FEATURE_PRESENT (AVX512_VPOPCNTDQ); > + CHECK_CPU_FEATURE_PRESENT (LA57); > CHECK_CPU_FEATURE_PRESENT (RDPID); > CHECK_CPU_FEATURE_PRESENT (KL); > CHECK_CPU_FEATURE_PRESENT (CLDEMOTE); > -- > 2.39.2 > Rename: `#define bit_cpu_INDEX_7_ECX_16` in cpu-features.h?
On Wed, Apr 5, 2023 at 11:20 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote: > > On Wed, Apr 5, 2023 at 11:22 AM H.J. Lu via Libc-alpha > <libc-alpha@sourceware.org> wrote: > > > > Add 57-bit linear addresses and five-level paging (LA57) support to > > <sys/platform/x86.h>. > > --- > > manual/platform.texi | 3 +++ > > sysdeps/x86/bits/platform/x86.h | 2 +- > > sysdeps/x86/tst-get-cpu-features.c | 1 + > > 3 files changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/manual/platform.texi b/manual/platform.texi > > index c1cef570d2..9251b63e47 100644 > > --- a/manual/platform.texi > > +++ b/manual/platform.texi > > @@ -394,6 +394,9 @@ the indirect branch predictor barrier (IBPB). > > @item > > @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR. > > > > +@item > > +@code{LA57} -- 57-bit linear addresses and five-level paging. > > + > > @item > > @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode. > > > > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h > > index 1ed24d7024..c9189fa248 100644 > > --- a/sysdeps/x86/bits/platform/x86.h > > +++ b/sysdeps/x86/bits/platform/x86.h > > @@ -182,7 +182,7 @@ enum > > x86_cpu_INDEX_7_ECX_13 = x86_cpu_index_7_ecx + 13, > > x86_cpu_AVX512_VPOPCNTDQ = x86_cpu_index_7_ecx + 14, > > x86_cpu_INDEX_7_ECX_15 = x86_cpu_index_7_ecx + 15, > > - x86_cpu_INDEX_7_ECX_16 = x86_cpu_index_7_ecx + 16, > > + x86_cpu_LA57 = x86_cpu_index_7_ecx + 16, > > /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX > > instructions in 64-bit mode. */ > > x86_cpu_RDPID = x86_cpu_index_7_ecx + 22, > > diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c > > index 1954698df8..5f5cd3e448 100644 > > --- a/sysdeps/x86/tst-get-cpu-features.c > > +++ b/sysdeps/x86/tst-get-cpu-features.c > > @@ -144,6 +144,7 @@ do_test (void) > > CHECK_CPU_FEATURE_PRESENT (AVX512_VNNI); > > CHECK_CPU_FEATURE_PRESENT (AVX512_BITALG); > > CHECK_CPU_FEATURE_PRESENT (AVX512_VPOPCNTDQ); > > + CHECK_CPU_FEATURE_PRESENT (LA57); > > CHECK_CPU_FEATURE_PRESENT (RDPID); > > CHECK_CPU_FEATURE_PRESENT (KL); > > CHECK_CPU_FEATURE_PRESENT (CLDEMOTE); > > -- > > 2.39.2 > > > Rename: > `#define bit_cpu_INDEX_7_ECX_16` > in cpu-features.h? cpu-features.h is used internally in glibc. Changes in cpu-features.h are needed only if we need to use CPU_FEATURE_SET_ACTIVE to mark a feature active.
On Wed, Apr 5, 2023 at 1:39 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Wed, Apr 5, 2023 at 11:20 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote: > > > > On Wed, Apr 5, 2023 at 11:22 AM H.J. Lu via Libc-alpha > > <libc-alpha@sourceware.org> wrote: > > > > > > Add 57-bit linear addresses and five-level paging (LA57) support to > > > <sys/platform/x86.h>. > > > --- > > > manual/platform.texi | 3 +++ > > > sysdeps/x86/bits/platform/x86.h | 2 +- > > > sysdeps/x86/tst-get-cpu-features.c | 1 + > > > 3 files changed, 5 insertions(+), 1 deletion(-) > > > > > > diff --git a/manual/platform.texi b/manual/platform.texi > > > index c1cef570d2..9251b63e47 100644 > > > --- a/manual/platform.texi > > > +++ b/manual/platform.texi > > > @@ -394,6 +394,9 @@ the indirect branch predictor barrier (IBPB). > > > @item > > > @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR. > > > > > > +@item > > > +@code{LA57} -- 57-bit linear addresses and five-level paging. > > > + > > > @item > > > @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode. > > > > > > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h > > > index 1ed24d7024..c9189fa248 100644 > > > --- a/sysdeps/x86/bits/platform/x86.h > > > +++ b/sysdeps/x86/bits/platform/x86.h > > > @@ -182,7 +182,7 @@ enum > > > x86_cpu_INDEX_7_ECX_13 = x86_cpu_index_7_ecx + 13, > > > x86_cpu_AVX512_VPOPCNTDQ = x86_cpu_index_7_ecx + 14, > > > x86_cpu_INDEX_7_ECX_15 = x86_cpu_index_7_ecx + 15, > > > - x86_cpu_INDEX_7_ECX_16 = x86_cpu_index_7_ecx + 16, > > > + x86_cpu_LA57 = x86_cpu_index_7_ecx + 16, > > > /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX > > > instructions in 64-bit mode. */ > > > x86_cpu_RDPID = x86_cpu_index_7_ecx + 22, > > > diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c > > > index 1954698df8..5f5cd3e448 100644 > > > --- a/sysdeps/x86/tst-get-cpu-features.c > > > +++ b/sysdeps/x86/tst-get-cpu-features.c > > > @@ -144,6 +144,7 @@ do_test (void) > > > CHECK_CPU_FEATURE_PRESENT (AVX512_VNNI); > > > CHECK_CPU_FEATURE_PRESENT (AVX512_BITALG); > > > CHECK_CPU_FEATURE_PRESENT (AVX512_VPOPCNTDQ); > > > + CHECK_CPU_FEATURE_PRESENT (LA57); > > > CHECK_CPU_FEATURE_PRESENT (RDPID); > > > CHECK_CPU_FEATURE_PRESENT (KL); > > > CHECK_CPU_FEATURE_PRESENT (CLDEMOTE); > > > -- > > > 2.39.2 > > > > > Rename: > > `#define bit_cpu_INDEX_7_ECX_16` > > in cpu-features.h? > > cpu-features.h is used internally in glibc. Changes in > cpu-features.h are needed only if we need to use > CPU_FEATURE_SET_ACTIVE to mark a feature active. > > -- > H.J. LGTM Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
diff --git a/manual/platform.texi b/manual/platform.texi index c1cef570d2..9251b63e47 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -394,6 +394,9 @@ the indirect branch predictor barrier (IBPB). @item @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR. +@item +@code{LA57} -- 57-bit linear addresses and five-level paging. + @item @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode. diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h index 1ed24d7024..c9189fa248 100644 --- a/sysdeps/x86/bits/platform/x86.h +++ b/sysdeps/x86/bits/platform/x86.h @@ -182,7 +182,7 @@ enum x86_cpu_INDEX_7_ECX_13 = x86_cpu_index_7_ecx + 13, x86_cpu_AVX512_VPOPCNTDQ = x86_cpu_index_7_ecx + 14, x86_cpu_INDEX_7_ECX_15 = x86_cpu_index_7_ecx + 15, - x86_cpu_INDEX_7_ECX_16 = x86_cpu_index_7_ecx + 16, + x86_cpu_LA57 = x86_cpu_index_7_ecx + 16, /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode. */ x86_cpu_RDPID = x86_cpu_index_7_ecx + 22, diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c index 1954698df8..5f5cd3e448 100644 --- a/sysdeps/x86/tst-get-cpu-features.c +++ b/sysdeps/x86/tst-get-cpu-features.c @@ -144,6 +144,7 @@ do_test (void) CHECK_CPU_FEATURE_PRESENT (AVX512_VNNI); CHECK_CPU_FEATURE_PRESENT (AVX512_BITALG); CHECK_CPU_FEATURE_PRESENT (AVX512_VPOPCNTDQ); + CHECK_CPU_FEATURE_PRESENT (LA57); CHECK_CPU_FEATURE_PRESENT (RDPID); CHECK_CPU_FEATURE_PRESENT (KL); CHECK_CPU_FEATURE_PRESENT (CLDEMOTE);