From patchwork Wed Nov 23 15:14:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rainer Orth X-Patchwork-Id: 127322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 1CC961007D4 for ; Thu, 24 Nov 2011 02:14:31 +1100 (EST) Received: (qmail 18131 invoked by alias); 23 Nov 2011 15:14:27 -0000 Received: (qmail 18122 invoked by uid 22791); 23 Nov 2011 15:14:26 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, T_TVD_MIME_NO_HEADERS X-Spam-Check-By: sourceware.org Received: from snape.CeBiTec.Uni-Bielefeld.DE (HELO smtp-relay.CeBiTec.Uni-Bielefeld.DE) (129.70.160.84) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 23 Nov 2011 15:14:10 +0000 Received: from localhost (localhost.CeBiTec.Uni-Bielefeld.DE [127.0.0.1]) by smtp-relay.CeBiTec.Uni-Bielefeld.DE (Postfix) with ESMTP id B7110591; Wed, 23 Nov 2011 16:14:08 +0100 (CET) Received: from smtp-relay.CeBiTec.Uni-Bielefeld.DE ([127.0.0.1]) by localhost (malfoy.CeBiTec.Uni-Bielefeld.DE [127.0.0.1]) (amavisd-new, port 10024) with LMTP id If+feG9SBmeg; Wed, 23 Nov 2011 16:14:05 +0100 (CET) Received: from manam.CeBiTec.Uni-Bielefeld.DE (manam.CeBiTec.Uni-Bielefeld.DE [129.70.161.120]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp-relay.CeBiTec.Uni-Bielefeld.DE (Postfix) with ESMTPS id 93FB0590; Wed, 23 Nov 2011 16:14:05 +0100 (CET) Received: (from ro@localhost) by manam.CeBiTec.Uni-Bielefeld.DE (8.14.5+Sun/8.14.5/Submit) id pANFE4NS016734; Wed, 23 Nov 2011 16:14:04 +0100 (MET) From: Rainer Orth To: gcc-patches@gcc.gnu.org Cc: Andrew Macleod , Uros Bizjak Subject: [testsuite] Fix several atomic tests on 32-bit x86 (PR testsuite/51258) Date: Wed, 23 Nov 2011 16:14:04 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (usg-unix-v) MIME-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org As described in the PR, several atomic tests were failing on bi-arch 32-bit x86 for the 64-bit multilib. As Uros found, this is obvious and corrected by the following patch, which also fixes a typo in atomic-other-int128.c. Tested with the appropriate runtest invocations on i386-pc-solaris2.10 and amd64-pc-solaris2.10, no change on the latter, the 64-bit tests pass now (or are unsupported for the simulate-thread tests with gdb 7.1; those fail instead with gdb 7.3.1 ;-). Ok for mainline? Rainer 2011-11-23 Rainer Orth PR testsuite/51258 * gcc.dg/atomic-compare-exchange-5.c: Add -mcx16 on i?86-*-*. * gcc.dg/atomic-exchange-5.c: Likewise. * gcc.dg/atomic-load-5.c: Likewise. * gcc.dg/atomic-op-5.c: Likewise. * gcc.dg/atomic-store-5.c: Likewise. * gcc.dg/simulate-thread/atomic-other-int128.c: Fix typo. # HG changeset patch # Parent ad316ae6941ee37a3133fc84f8281ae9c07ebefa Fix several atomic tests on 32-bit x86 (PR testsuite/51258) diff --git a/gcc/testsuite/gcc.dg/atomic-compare-exchange-5.c b/gcc/testsuite/gcc.dg/atomic-compare-exchange-5.c --- a/gcc/testsuite/gcc.dg/atomic-compare-exchange-5.c +++ b/gcc/testsuite/gcc.dg/atomic-compare-exchange-5.c @@ -2,7 +2,7 @@ values with each valid memory model. */ /* { dg-do run } */ /* { dg-require-effective-target sync_int_128 } */ -/* { dg-options "-mcx16" { target { x86_64-*-* } } } */ +/* { dg-options "-mcx16" { target { i?86-*-* x86_64-*-* } } } */ /* Test the execution of __atomic_compare_exchange_n builtin for an int_128. */ diff --git a/gcc/testsuite/gcc.dg/atomic-exchange-5.c b/gcc/testsuite/gcc.dg/atomic-exchange-5.c --- a/gcc/testsuite/gcc.dg/atomic-exchange-5.c +++ b/gcc/testsuite/gcc.dg/atomic-exchange-5.c @@ -2,7 +2,7 @@ values with each valid memory model. */ /* { dg-do run } */ /* { dg-require-effective-target sync_int_128 } */ -/* { dg-options "-mcx16" { target { x86_64-*-* } } } */ +/* { dg-options "-mcx16" { target { i?86-*-* x86_64-*-* } } } */ /* Test the execution of the __atomic_X builtin for a 16 byte value. */ diff --git a/gcc/testsuite/gcc.dg/atomic-load-5.c b/gcc/testsuite/gcc.dg/atomic-load-5.c --- a/gcc/testsuite/gcc.dg/atomic-load-5.c +++ b/gcc/testsuite/gcc.dg/atomic-load-5.c @@ -2,7 +2,7 @@ values with each valid memory model. */ /* { dg-do run } */ /* { dg-require-effective-target sync_int_128 } */ -/* { dg-options "-mcx16" { target { x86_64-*-* } } } */ +/* { dg-options "-mcx16" { target { i?86-*-* x86_64-*-* } } } */ extern void abort(void); diff --git a/gcc/testsuite/gcc.dg/atomic-op-5.c b/gcc/testsuite/gcc.dg/atomic-op-5.c --- a/gcc/testsuite/gcc.dg/atomic-op-5.c +++ b/gcc/testsuite/gcc.dg/atomic-op-5.c @@ -2,7 +2,7 @@ values with each valid memory model. */ /* { dg-do run } */ /* { dg-require-effective-target sync_int_128 } */ -/* { dg-options "-mcx16" { target { x86_64-*-* } } } */ +/* { dg-options "-mcx16" { target { i?86-*-* x86_64-*-* } } } */ /* Test the execution of the __atomic_*OP builtin routines for an int_128. */ diff --git a/gcc/testsuite/gcc.dg/atomic-store-5.c b/gcc/testsuite/gcc.dg/atomic-store-5.c --- a/gcc/testsuite/gcc.dg/atomic-store-5.c +++ b/gcc/testsuite/gcc.dg/atomic-store-5.c @@ -2,7 +2,7 @@ values with each valid memory model. */ /* { dg-do run } */ /* { dg-require-effective-target sync_int_128 } */ -/* { dg-options "-mcx16" { target { x86_64-*-* } } } */ +/* { dg-options "-mcx16" { target { i?86-*-* x86_64-*-* } } } */ /* Test the execution of the __atomic_store_n builtin for a 16 byte value. */ diff --git a/gcc/testsuite/gcc.dg/simulate-thread/atomic-other-int128.c b/gcc/testsuite/gcc.dg/simulate-thread/atomic-other-int128.c --- a/gcc/testsuite/gcc.dg/simulate-thread/atomic-other-int128.c +++ b/gcc/testsuite/gcc.dg/simulate-thread/atomic-other-int128.c @@ -1,6 +1,6 @@ /* { dg-do link } */ /* { dg-require-effective-target sync_int_128 } */ -/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-*] } } } */ +/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-* } } } */ /* { dg-final { simulate-thread } } */ #include