From patchwork Wed Apr 14 15:21:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1466291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=K/FHOgBc; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FL5mD0Xm9z9sRR for ; Thu, 15 Apr 2021 01:21:30 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 09BEB395C402; Wed, 14 Apr 2021 15:21:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 09BEB395C402 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1618413688; bh=LDcJZXaXnXinzTa5q2FVqNl7Up5oK9S5XaRtKwufvmY=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=K/FHOgBcAXD5Ohw87rqopjGJ/utRS2l9Bcm2PaOTz+9kTN+vAVaWg0QF2ayGNld+B wDcO0+Y7jUXtUFTdmg6qVVkMJ0yCCkyjPX3ywxbBZWxcSRV2WxP6cMlCYwDlMa7mEO MGbH6XSdhcZrMAuUZW3jabzGQqRrCKBTTuhtfics= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2A0243954C13 for ; Wed, 14 Apr 2021 15:21:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 2A0243954C13 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CAA7C113E for ; Wed, 14 Apr 2021 08:21:24 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.126]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 71ABE3F73B for ; Wed, 14 Apr 2021 08:21:24 -0700 (PDT) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH] aarch64: Handle more SVE vector constants [PR99246] Date: Wed, 14 Apr 2021 16:21:23 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" PR99246 is about a case in which we failed to handle a CONST_VECTOR with NELTS_PER_PATTERN==2, i.e. a vector with a “foreground” sequence of N vectors followed by a repeating “background” sequence of N vectors. At the moment, it's difficult to produce these vectors directly, but I'm hoping that for GCC 12 we'll do more folding, which will in turn make this easier to test and easier to optimise. Until then, the patch simply relies on the testcase in the PR. Tested on aarch64-linux-gnu, pushed to trunk so far. Richard gcc/ PR target/99246 * config/aarch64/aarch64.c (aarch64_expand_sve_const_vector_sel): New function. (aarch64_expand_sve_const_vector): Use it for nelts_per_pattern==2. gcc/testsuite/ PR target/99246 * gcc.target/aarch64/sve/acle/general/pr99246.c: New test. --- gcc/config/aarch64/aarch64.c | 54 +++++++++++++++++++ .../aarch64/sve/acle/general/pr99246.c | 17 ++++++ 2 files changed, 71 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr99246.c diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 640550419dc..04b55d9070b 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5166,6 +5166,56 @@ aarch64_expand_sve_ld1rq (rtx dest, rtx src) return true; } +/* SRC is an SVE CONST_VECTOR that contains N "foreground" values followed + by N "background" values. Try to move it into TARGET using: + + PTRUE PRED., VL + MOV TRUE., # + MOV FALSE., # + SEL TARGET., PRED., TRUE., FALSE. + + The PTRUE is always a single instruction but the MOVs might need a + longer sequence. If the background value is zero (as it often is), + the sequence can sometimes collapse to a PTRUE followed by a + zero-predicated move. + + Return the target on success, otherwise return null. */ + +static rtx +aarch64_expand_sve_const_vector_sel (rtx target, rtx src) +{ + gcc_assert (CONST_VECTOR_NELTS_PER_PATTERN (src) == 2); + + /* Make sure that the PTRUE is valid. */ + machine_mode mode = GET_MODE (src); + machine_mode pred_mode = aarch64_sve_pred_mode (mode); + unsigned int npatterns = CONST_VECTOR_NPATTERNS (src); + if (aarch64_svpattern_for_vl (pred_mode, npatterns) + == AARCH64_NUM_SVPATTERNS) + return NULL_RTX; + + rtx_vector_builder pred_builder (pred_mode, npatterns, 2); + rtx_vector_builder true_builder (mode, npatterns, 1); + rtx_vector_builder false_builder (mode, npatterns, 1); + for (unsigned int i = 0; i < npatterns; ++i) + { + true_builder.quick_push (CONST_VECTOR_ENCODED_ELT (src, i)); + pred_builder.quick_push (CONST1_RTX (BImode)); + } + for (unsigned int i = 0; i < npatterns; ++i) + { + false_builder.quick_push (CONST_VECTOR_ENCODED_ELT (src, i + npatterns)); + pred_builder.quick_push (CONST0_RTX (BImode)); + } + expand_operand ops[4]; + create_output_operand (&ops[0], target, mode); + create_input_operand (&ops[1], true_builder.build (), mode); + create_input_operand (&ops[2], false_builder.build (), mode); + create_input_operand (&ops[3], pred_builder.build (), pred_mode); + expand_insn (code_for_vcond_mask (mode, mode), 4, ops); + return target; +} + /* Return a register containing CONST_VECTOR SRC, given that SRC has an SVE data mode and isn't a legitimate constant. Use TARGET for the result if convenient. @@ -5300,6 +5350,10 @@ aarch64_expand_sve_const_vector (rtx target, rtx src) if (GET_MODE_NUNITS (mode).is_constant ()) return NULL_RTX; + if (nelts_per_pattern == 2) + if (rtx res = aarch64_expand_sve_const_vector_sel (target, src)) + return res; + /* Expand each pattern individually. */ gcc_assert (npatterns > 1); rtx_vector_builder builder; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr99246.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr99246.c new file mode 100644 index 00000000000..7f1079c1bd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr99246.c @@ -0,0 +1,17 @@ +/* { dg-options "-Os" } */ + +#include +extern char b[]; +int x; +void f() { + while (x) { + x = svaddv( + svnot_z(svnot_z(svptrue_pat_b8(SV_VL6), + svmov_z(svptrue_pat_b8(SV_VL1), + svptrue_pat_b16(SV_VL3))), + svptrue_pat_b64(SV_VL2)), + svdup_s32(8193)); + for (int j = x; j; j++) + b[j] = 0; + } +}