@@ -129,6 +129,8 @@ AARCH64_OPT_EXTENSION("sve2-sha3", SVE2_SHA3, (SVE2, SHA3), (), (), "svesha3")
AARCH64_OPT_EXTENSION("sve2-bitperm", SVE2_BITPERM, (SVE2), (), (),
"svebitperm")
+AARCH64_OPT_EXTENSION("sme", SME, (SVE2), (), (), "sme")
+
AARCH64_OPT_EXTENSION("tme", TME, (), (), (), "")
AARCH64_OPT_EXTENSION("i8mm", I8MM, (SIMD), (), (), "i8mm")
@@ -11374,6 +11374,23 @@ aarch64_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
return true;
}
+/* Implement TARGET_START_CALL_ARGS. */
+
+static void
+aarch64_start_call_args (cumulative_args_t ca_v)
+{
+ CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
+
+ if (!TARGET_SME && (ca->isa_mode & AARCH64_FL_SM_ON))
+ {
+ error ("calling a streaming function requires the ISA extension %qs",
+ "sme");
+ inform (input_location, "you can enable %qs using the command-line"
+ " option %<-march%>, or by using the %<target%>"
+ " attribute or pragma", "sme");
+ }
+}
+
/* This function is used by the call expanders of the machine description.
RESULT is the register in which the result is returned. It's NULL for
"call" and "sibcall".
@@ -17865,6 +17882,19 @@ aarch64_override_options_internal (struct gcc_options *opts)
&& !fixed_regs[R18_REGNUM])
error ("%<-fsanitize=shadow-call-stack%> requires %<-ffixed-x18%>");
+ if ((opts->x_aarch64_isa_flags & AARCH64_FL_SM_ON)
+ && !(opts->x_aarch64_isa_flags & AARCH64_FL_SME))
+ {
+ error ("streaming functions require the ISA extension %qs", "sme");
+ inform (input_location, "you can enable %qs using the command-line"
+ " option %<-march%>, or by using the %<target%>"
+ " attribute or pragma", "sme");
+ opts->x_target_flags &= ~MASK_GENERAL_REGS_ONLY;
+ auto new_flags = (opts->x_aarch64_asm_isa_flags
+ | feature_deps::SME ().enable);
+ aarch64_set_asm_isa_flags (opts, new_flags);
+ }
+
initialize_aarch64_code_model (opts);
initialize_aarch64_tls_size (opts);
@@ -27721,6 +27751,9 @@ aarch64_run_selftests (void)
#undef TARGET_FUNCTION_VALUE_REGNO_P
#define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
+#undef TARGET_START_CALL_ARGS
+#define TARGET_START_CALL_ARGS aarch64_start_call_args
+
#undef TARGET_GIMPLE_FOLD_BUILTIN
#define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
@@ -214,6 +214,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
#define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM)
#define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3)
#define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4)
+#define AARCH64_ISA_SME (aarch64_isa_flags & AARCH64_FL_SME)
#define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A)
#define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD)
#define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES)
@@ -544,6 +544,9 @@ the following and their inverses no :samp:`{feature}` :
:samp:`pauth`
Enable the Pointer Authentication Extension.
+:samp:`sme`
+ Enable the Scalable Matrix Extension.
+
Feature ``crypto`` implies ``aes``, ``sha2``, and ``simd``,
which implies ``fp``.
Conversely, ``nofp`` implies ``nosimd``, which implies
@@ -886,6 +886,9 @@ AArch64-specific attributes
AArch64 target that is able to generate and execute armv8.3-a FJCVTZS
instruction.
+``aarch64_sme``
+ AArch64 target that generates instructions for SME.
+
MIPS-specific attributes
~~~~~~~~~~~~~~~~~~~~~~~~
@@ -31,10 +31,16 @@ load_lib gcc-dg.exp
# Initialize `dg'.
dg-init
-aarch64-with-arch-dg-options "" {
+if { [check_effective_target_aarch64_sme] } {
+ set sme_flags ""
+} else {
+ set sme_flags "-march=armv8.2-a+sme"
+}
+
+aarch64-with-arch-dg-options $sme_flags {
# Main loop.
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
- "" ""
+ "" $sme_flags
}
# All done.
new file mode 100644
@@ -0,0 +1,63 @@
+// { dg-options "" }
+
+#pragma GCC target "+nosme"
+
+void __attribute__((arm_streaming_compatible)) sc_a () {}
+void __attribute__((arm_streaming)) s_a () {} // { dg-error "streaming functions require the ISA extension 'sme'" }
+void ns_a () {}
+
+void __attribute__((arm_streaming_compatible)) sc_b () {}
+void ns_b () {}
+void __attribute__((arm_streaming)) s_b () {} // { dg-error "streaming functions require the ISA extension 'sme'" }
+
+void __attribute__((arm_streaming_compatible)) sc_c () {}
+void __attribute__((arm_streaming_compatible)) sc_d () {}
+
+void __attribute__((arm_streaming)) s_c () {} // { dg-error "streaming functions require the ISA extension 'sme'" }
+void __attribute__((arm_streaming)) s_d () {} // { dg-error "streaming functions require the ISA extension 'sme'" }
+
+void ns_c () {}
+void ns_d () {}
+
+void __attribute__((arm_streaming_compatible)) sc_e ();
+void __attribute__((arm_streaming)) s_e ();
+void ns_e ();
+
+#pragma GCC target "+sme"
+
+void __attribute__((arm_streaming_compatible)) sc_f () {}
+void __attribute__((arm_streaming)) s_f () {}
+void ns_f () {}
+
+void __attribute__((arm_streaming_compatible)) sc_g () {}
+void ns_g () {}
+void __attribute__((arm_streaming)) s_g () {}
+
+void __attribute__((arm_streaming_compatible)) sc_h () {}
+void __attribute__((arm_streaming_compatible)) sc_i () {}
+
+void __attribute__((arm_streaming)) s_h () {}
+void __attribute__((arm_streaming)) s_i () {}
+
+void ns_h () {}
+void ns_i () {}
+
+void __attribute__((arm_streaming_compatible)) sc_j ();
+void __attribute__((arm_streaming)) s_j ();
+void ns_j ();
+
+#pragma GCC target "+sme"
+
+void __attribute__((arm_streaming_compatible)) sc_k () {}
+
+#pragma GCC target "+nosme"
+#pragma GCC target "+sme"
+
+void __attribute__((arm_streaming)) s_k () {}
+
+#pragma GCC target "+nosme"
+#pragma GCC target "+sme"
+
+void ns_k () {}
+
+#pragma GCC target "+nosme"
new file mode 100644
@@ -0,0 +1,22 @@
+// { dg-options "-mgeneral-regs-only" }
+
+void __attribute__((arm_streaming_compatible)) sc_a () {}
+void __attribute__((arm_streaming)) s_a () {} // { dg-error "streaming functions require the ISA extension 'sme'" }
+void ns_a () {}
+
+void __attribute__((arm_streaming_compatible)) sc_b () {}
+void ns_b () {}
+void __attribute__((arm_streaming)) s_b () {} // { dg-error "streaming functions require the ISA extension 'sme'" }
+
+void __attribute__((arm_streaming_compatible)) sc_c () {}
+void __attribute__((arm_streaming_compatible)) sc_d () {}
+
+void __attribute__((arm_streaming)) s_c () {} // { dg-error "streaming functions require the ISA extension 'sme'" }
+void __attribute__((arm_streaming)) s_d () {} // { dg-error "streaming functions require the ISA extension 'sme'" }
+
+void ns_c () {}
+void ns_d () {}
+
+void __attribute__((arm_streaming_compatible)) sc_e ();
+void __attribute__((arm_streaming)) s_e ();
+void ns_e ();
@@ -3967,6 +3967,18 @@ proc aarch64_sve_bits { } {
}]
}
+# Return 1 if this is an AArch64 target that generates instructions for SME.
+proc check_effective_target_aarch64_sme { } {
+ if { ![istarget aarch64*-*-*] } {
+ return 0
+ }
+ return [check_no_compiler_messages aarch64_sme assembly {
+ #if !defined (__ARM_FEATURE_SME)
+ #error FOO
+ #endif
+ }]
+}
+
# Return 1 if this is a compiler supporting ARC atomic operations
proc check_effective_target_arc_atomic { } {
return [check_no_compiler_messages arc_atomic assembly {