From patchwork Tue May 21 16:26:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1102923 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-501369-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="TBkTDPOu"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 457h4z6q7Tz9s7h for ; Wed, 22 May 2019 02:27:47 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=vvooNGQkcc0XgNqtCYZ PML1cVk6JoXzGEmJ19yMyI5KLZyry5P0BjNfJBeZZuh55LcsgzbaSqEsqK7xeMLm XnB70FiEqqMACDGG06/cJDRfM4pH2OhpqCGKafwUYzPvpdQFEcqBwbl52VMH3kT/ eFwf8qd0+yS8JxIEUUx8lgzo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=Nj6d+3m9lDiHTT1fl1zkLNQnQ S4=; b=TBkTDPOu0ySqJwk2x5/AzFo/n7/Dxo2xEM6bLNvyzTzlAF7ewq4Cb59VR /aKLB4qOt+Dfkyi2NR0aroqOVmYbcSXnYcaxxdhf9OpHpIY44e3IZcIYJzDfFcLw r0Gq7Yy5dzCs1g15P9m22vvbBSh3c8LscWw/pIjIpxEHlFKadc= Received: (qmail 81127 invoked by alias); 21 May 2019 16:27:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81076 invoked by uid 89); 21 May 2019 16:27:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 May 2019 16:27:18 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 033DE1240630; Tue, 21 May 2019 16:27:16 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 3/6] rs6000: wk -> ws+p8v Date: Tue, 21 May 2019 16:26:57 +0000 Message-Id: In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes 2019-05-21 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wk"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wk. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wk" constraint by "ws" with "p8v". * doc/md.texi (Machine Constraints): Adjust. --- gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/rs6000.c | 9 +-------- gcc/config/rs6000/rs6000.h | 1 - gcc/config/rs6000/rs6000.md | 2 +- gcc/doc/md.texi | 5 +---- 5 files changed, 3 insertions(+), 17 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 9f315e4..6f60627 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -74,9 +74,6 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") -(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" - "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") - (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 76c80a4..718535f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void) "wf reg_class = %s\n" "wg reg_class = %s\n" "wi reg_class = %s\n" - "wk reg_class = %s\n" "wl reg_class = %s\n" "wm reg_class = %s\n" "wp reg_class = %s\n" @@ -2536,7 +2535,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], @@ -3160,7 +3158,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) wf - Preferred register class for V4SFmode. wg - Float register for power6x move insns. wi - FP or VSX register to hold 64-bit integers for VSX insns. - wk - FP or VSX register to hold 64-bit doubles for direct moves. wl - Float register if we can do 32-bit signed int loads. wm - VSX register for ISA 2.07 direct move operations. wn - always NO_REGS. @@ -3201,11 +3198,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */ if (TARGET_DIRECT_MOVE) - { - rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */ - = rs6000_constraints[RS6000_CONSTRAINT_ws]; - rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; - } + rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; if (TARGET_POWERPC64) { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 218ed10..cc60559 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ - RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wm, /* VSX register for direct move */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9a986a1..33a6de7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -471,7 +471,7 @@ (define_mode_attr zero_fp [(SF "j") (define_mode_attr f64_vsx [(DF "ws") (DD "wn")]) ; Definitions for 64-bit direct move -(define_mode_attr f64_dm [(DF "wk") (DD "d")]) +(define_mode_attr f64_dm [(DF "ws") (DD "d")]) ; Definitions for 64-bit use of altivec registers (define_mode_attr f64_av [(DF "wv") (DD "wn")]) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 55de2f1..13a621d 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3197,7 +3197,7 @@ Altivec vector register Any VSX register if the @option{-mvsx} option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, -@code{wf}, @code{wg}, @code{wi}, @code{wk}, +@code{wf}, @code{wg}, @code{wi}, @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wt}, @code{wv}, or @code{ww}) that take VSX registers, you must use @code{%x} in the template so @@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS. @item wi FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS. -@item wk -FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS. - @item wl Floating point register if the LFIWAX instruction is enabled or NO_REGS.