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[committed,amdgcn] Add sub-dword vector multiply

Message ID f65673c0-71b1-92f5-d09e-95ddb6c96301@codesourcery.com
State New
Headers show
Series [committed,amdgcn] Add sub-dword vector multiply | expand

Commit Message

Andrew Stubbs Dec. 13, 2019, 4:39 p.m. UTC 
I've committed this patch to add v64qi and v64hi multiply patterns.

This is slowly working toward full char and short vectorization.

Andrew
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Patch

Sub-dword vector multiply for amdgcn

2019-12-13  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (mulv64si3<exec>): Rename to ...
	(mul<mode>3<exec>): ... this, and implement sub-dword patterns.
	(mulv64si3_dup<exec>): Rename to ...
	(mul<mode>3_dup<exec>): ... this, and implement sub-dword patterns.

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index e1b3c71971f..42604466161 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -1740,22 +1740,22 @@ 
   [(set_attr "type" "vop3a")
    (set_attr "length" "8")])
 
-(define_insn "mulv64si3<exec>"
-  [(set (match_operand:V64SI 0 "register_operand"  "=   v")
-	(mult:V64SI
-	  (match_operand:V64SI 1 "gcn_alu_operand" "%vSvA")
-	  (match_operand:V64SI 2 "gcn_alu_operand" " vSvA")))]
+(define_insn "mul<mode>3<exec>"
+  [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand"  "=   v")
+	(mult:VEC_ALL1REG_INT_MODE
+	  (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA")
+	  (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_operand" " vSvA")))]
   ""
   "v_mul_lo_u32\t%0, %1, %2"
   [(set_attr "type" "vop3a")
    (set_attr "length" "8")])
 
-(define_insn "mulv64si3_dup<exec>"
-  [(set (match_operand:V64SI 0 "register_operand"  "=   v")
-	(mult:V64SI
-	  (match_operand:V64SI 1 "gcn_alu_operand" "%vSvA")
-	  (vec_duplicate:V64SI
-	    (match_operand:SI 2 "gcn_alu_operand"  "  SvA"))))]
+(define_insn "mul<mode>3_dup<exec>"
+  [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand"  "=   v")
+	(mult:VEC_ALL1REG_INT_MODE
+	  (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" "%vSvA")
+	  (vec_duplicate:VEC_ALL1REG_INT_MODE
+	    (match_operand:<SCALAR_MODE> 2 "gcn_alu_operand"	  "  SvA"))))]
   ""
   "v_mul_lo_u32\t%0, %1, %2"
   [(set_attr "type" "vop3a")