@@ -37,9 +37,9 @@ (define_insn_reservation "ppc403-store" 2
"iu_40x")
(define_insn_reservation "ppc403-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,trap,\
cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
@@ -57,7 +57,7 @@ (define_insn_reservation "ppc403-three" 1
(define_insn_reservation "ppc403-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
@@ -54,9 +54,9 @@ (define_insn_reservation "ppc440-fpstore" 3
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,\
trap,cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
@@ -64,8 +64,8 @@ (define_insn_reservation "ppc476-fpstore" 4
ppc476_lj_pipe")
(define_insn_reservation "ppc476-simple-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,exts,shift")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (ior (eq_attr "type" "integer,insert_word,exts")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
@@ -80,7 +80,7 @@ (define_insn_reservation "ppc476-complex-integer" 1
(define_insn_reservation "ppc476-compare" 4
(and (ior (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\
mtcr,mfjmpr,mtjmpr,var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
@@ -46,9 +46,9 @@ (define_insn_reservation "ppc601-fpstore" 3
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,\
trap,cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601")
@@ -77,7 +77,7 @@ (define_insn_reservation "ppc601-idiv" 36
; execute on the branch unit.
(define_insn_reservation "ppc601-compare" 3
(and (ior (eq_attr "type" "cmp,compare,delayed_compare,var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc601"))
"iu_ppc601,nothing,bpu_ppc601")
@@ -58,9 +58,9 @@ (define_insn_reservation "ppc603-storec" 8
"lsu_603")
(define_insn_reservation "ppc603-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,trap,\
cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
@@ -94,7 +94,7 @@ (define_insn_reservation "ppc603-idiv" 37
(define_insn_reservation "ppc603-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
@@ -73,9 +73,9 @@ (define_insn_reservation "ppc630-llsc" 4
"lsu_6xx")
(define_insn_reservation "ppc604-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,trap,\
cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
@@ -143,7 +143,7 @@ (define_insn_reservation "ppc620-ldiv" 37
(define_insn_reservation "ppc604-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
@@ -74,9 +74,9 @@ (define_insn_reservation "ppc7450-sync" 35
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,\
trap,cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
@@ -110,7 +110,7 @@ (define_insn_reservation "ppc7450-idiv" 23
(define_insn_reservation "ppc7450-compare" 2
(and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
@@ -64,9 +64,9 @@ (define_insn_reservation "ppc750-storec" 8
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,\
trap,cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
@@ -104,7 +104,7 @@ (define_insn_reservation "ppc750-idiv" 19
(define_insn_reservation "ppc750-compare" 2
(and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
@@ -155,8 +155,8 @@ (define_insn_reservation "cell-vecstore" 1
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
- (and (ior (eq_attr "type" "integer,insert_dword,shift,trap,cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (ior (eq_attr "type" "integer,insert_dword,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "cell"))
"slot01,fxu_cell")
@@ -189,7 +189,7 @@ (define_insn_reservation "cell-cmp" 1
(define_insn_reservation "cell-fast-cmp" 2
(and (ior (eq_attr "type" "fast_compare,delayed_compare,compare,\
var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "not"))
@@ -198,7 +198,7 @@ (define_insn_reservation "cell-fast-cmp" 2
(define_insn_reservation "cell-cmp-microcoded" 9
(and (ior (eq_attr "type" "fast_compare,delayed_compare,compare,\
var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "always"))
@@ -75,7 +75,7 @@ (define_insn_reservation "e500mc64_su" 1
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
(define_insn_reservation "e500mc64_su2" 2
- (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare,trap")
+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
@@ -42,9 +42,9 @@ (define_insn_reservation "mpccore-fpload" 2
"lsu_mpc")
(define_insn_reservation "mpccore-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,trap,\
cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
@@ -73,7 +73,7 @@ (define_insn_reservation "mpccore-idiv" 6
(define_insn_reservation "mpccore-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
@@ -185,8 +185,8 @@ (define_insn_reservation "power4-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
- (and (ior (eq_attr "type" "integer,insert_dword,shift,trap,cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (ior (eq_attr "type" "integer,insert_dword,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power4"))
"iq_power4")
@@ -228,7 +228,7 @@ (define_insn_reservation "power4-cmp" 3
(define_insn_reservation "power4-compare" 2
(and (ior (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
@@ -141,9 +141,8 @@ (define_insn_reservation "power5-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
- (and (ior (eq_attr "type" "integer,insert_dword,shift,trap,\
- cntlz,exts,isel,popcnt")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (ior (eq_attr "type" "integer,insert_dword,trap,cntlz,exts,isel,popcnt")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power5"))
"iq_power5")
@@ -182,7 +181,7 @@ (define_insn_reservation "power5-cmp" 3
(define_insn_reservation "power5-compare" 2
(and (ior (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,iu2_power5")
@@ -213,6 +213,7 @@ (define_insn_reservation "power6-exts" 1
(define_insn_reservation "power6-shift" 1
(and (eq_attr "type" "shift")
+ (eq_attr "dot" "no")
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -323,7 +324,9 @@ (define_bypass 1 "power6-compare,\
"store_data_bypass_p")
(define_insn_reservation "power6-delayed-compare" 2 ; N/A
- (and (eq_attr "type" "delayed_compare")
+ (and (ior (eq_attr "type" "delayed_compare")
+ (and (eq_attr "type" "shift")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -149,9 +149,9 @@ (define_insn_reservation "power7-sync" 11
; FX Unit
(define_insn_reservation "power7-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,trap,\
exts,isel,popcnt")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
@@ -178,7 +178,7 @@ (define_insn_reservation "power7-cmp" 1
(define_insn_reservation "power7-compare" 2
(and (ior (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,FXU_power7")
@@ -23217,6 +23217,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
case TYPE_SHIFT:
+ case TYPE_DELAYED_COMPARE:
case TYPE_INSERT_WORD:
case TYPE_INSERT_DWORD:
case TYPE_FPLOAD_U:
@@ -23299,6 +23300,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
case TYPE_SHIFT:
+ case TYPE_DELAYED_COMPARE:
case TYPE_INSERT_WORD:
case TYPE_INSERT_DWORD:
case TYPE_FPLOAD_U:
@@ -23472,7 +23474,8 @@ is_cracked_insn (rtx insn)
|| type == TYPE_IDIV || type == TYPE_LDIV
|| type == TYPE_INSERT_WORD)
return true;
- if (get_attr_dot (insn) == DOT_YES && type == TYPE_VAR_SHIFT_ROTATE)
+ if (get_attr_dot (insn) == DOT_YES
+ && (type == TYPE_SHIFT || type == TYPE_VAR_SHIFT_ROTATE))
return true;
}
@@ -46,9 +46,9 @@ (define_insn_reservation "rs64a-llsc" 2
"lsu_rs64")
(define_insn_reservation "rs64a-integer" 1
- (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
+ (and (ior (eq_attr "type" "integer,insert_word,insert_dword,trap,\
cntlz,exts,isel")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "rs64a"))
"iu_rs64")
@@ -95,8 +95,8 @@ (define_insn_reservation "rs64a-ldiv" 66
(define_insn_reservation "rs64a-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare,\
- delayed_compare,var_delayed_compare")
- (and (eq_attr "type" "var_shift_rotate")
+ delayed_compare,var_delayed_compare")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")
@@ -55,8 +55,8 @@ (define_insn_reservation "titan_mulhw" 4
(define_bypass 2 "titan_mulhw" "titan_mulhw")
(define_insn_reservation "titan_fxu_shift_and_rotate" 2
- (and (ior (eq_attr "type" "insert_word,shift,cntlz")
- (and (eq_attr "type" "var_shift_rotate")
+ (and (ior (eq_attr "type" "insert_word,cntlz")
+ (and (eq_attr "type" "shift,var_shift_rotate")
(eq_attr "dot" "no")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")