Message ID | e8fed607-eb85-14ab-5295-018dd4716f97@linux.ibm.com |
---|---|
State | New |
Headers | show |
Series | [v2] rs6000: Disable HTM for Power10 and later | expand |
Hi! On Mon, Nov 30, 2020 at 06:36:30PM +0800, Kewen.Lin wrote: > --- a/gcc/config/rs6000/rs6000-cpus.def > +++ b/gcc/config/rs6000/rs6000-cpus.def > @@ -51,7 +51,6 @@ > | OPTION_MASK_CRYPTO \ > | OPTION_MASK_DIRECT_MOVE \ > | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ > - | OPTION_MASK_HTM \ > | OPTION_MASK_QUAD_MEMORY \ > | OPTION_MASK_QUAD_MEMORY_ATOMIC) (this is in #define ISA_2_7_MASKS_SERVER) That looks fine. > -RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) > -RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER) > +RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER > + | OPTION_MASK_HTM) > +RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER > + | OPTION_MASK_HTM) > -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) > +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER > + | OPTION_MASK_HTM) This, too. > --- a/gcc/config/rs6000/rs6000.c > +++ b/gcc/config/rs6000/rs6000.c > @@ -3807,7 +3807,8 @@ rs6000_option_override_internal (bool global_init_p) > /* If little-endian, default to -mstrict-align on older processors. > Testing for htm matches power8 and later. */ > if (!BYTES_BIG_ENDIAN > - && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) > + && !(processor_target_table[tune_index].target_enable > + & OPTION_MASK_CRYPTO)) > rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; But not this. Not all ISA 2.07 processors implement the crypto category. You could use OPTION_MASK_DIRECT_MOVE, instead? Okay for trunk with that change (if that works ;-) ) Thanks! Segher
Hi Segher, on 2020/12/1 上午4:49, Segher Boessenkool wrote: > Hi! > > On Mon, Nov 30, 2020 at 06:36:30PM +0800, Kewen.Lin wrote: >> --- a/gcc/config/rs6000/rs6000-cpus.def >> +++ b/gcc/config/rs6000/rs6000-cpus.def >> @@ -51,7 +51,6 @@ >> | OPTION_MASK_CRYPTO \ >> | OPTION_MASK_DIRECT_MOVE \ >> | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ >> - | OPTION_MASK_HTM \ >> | OPTION_MASK_QUAD_MEMORY \ >> | OPTION_MASK_QUAD_MEMORY_ATOMIC) > > (this is in #define ISA_2_7_MASKS_SERVER) > > That looks fine. > >> -RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) >> -RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER) >> +RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER >> + | OPTION_MASK_HTM) >> +RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER >> + | OPTION_MASK_HTM) > >> -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) >> +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER >> + | OPTION_MASK_HTM) > > This, too. > >> --- a/gcc/config/rs6000/rs6000.c >> +++ b/gcc/config/rs6000/rs6000.c >> @@ -3807,7 +3807,8 @@ rs6000_option_override_internal (bool global_init_p) >> /* If little-endian, default to -mstrict-align on older processors. >> Testing for htm matches power8 and later. */ >> if (!BYTES_BIG_ENDIAN >> - && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) >> + && !(processor_target_table[tune_index].target_enable >> + & OPTION_MASK_CRYPTO)) >> rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; > > But not this. Not all ISA 2.07 processors implement the crypto > category. You could use OPTION_MASK_DIRECT_MOVE, instead? > Thanks for the comments! Updated with OPTION_MASK_DIRECT_MOVE, re-testings passed and committed in r11-5645. BR, Kewen
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 8d2c1ffd6cf..482e1b69dde 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -51,7 +51,6 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ - | OPTION_MASK_HTM \ | OPTION_MASK_QUAD_MEMORY \ | OPTION_MASK_QUAD_MEMORY_ATOMIC) @@ -240,10 +239,13 @@ RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) -RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) -RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER) +RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER + | OPTION_MASK_HTM) +RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER + | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER + | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d8ac2f0cd2f..4f625d98078 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3807,7 +3807,8 @@ rs6000_option_override_internal (bool global_init_p) /* If little-endian, default to -mstrict-align on older processors. Testing for htm matches power8 and later. */ if (!BYTES_BIG_ENDIAN - && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) + && !(processor_target_table[tune_index].target_enable + & OPTION_MASK_CRYPTO)) rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; if (!rs6000_fold_gimple)