diff mbox

[2/3] Fix shift amount (GPR->SI)

Message ID e80a9cbccd496e91fc3538d1c4088d043df75405.1437404024.git.segher@kernel.crashing.org
State New
Headers show

Commit Message

Segher Boessenkool July 20, 2015, 4:04 p.m. UTC 
This changes the shift amount to always be SI (as it should be), not GPR.
It doesn't matter for constant shifts, but there are some variable shifts
as well, and consistency is good.

No changelog, I'll fold it into the previous big patch, if approved.


Segher

---
 gcc/config/rs6000/rs6000.md | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

Comments

David Edelsohn July 20, 2015, 4:19 p.m. UTC | #1 
On Mon, Jul 20, 2015 at 12:04 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> This changes the shift amount to always be SI (as it should be), not GPR.
> It doesn't matter for constant shifts, but there are some variable shifts
> as well, and consistency is good.
>
> No changelog, I'll fold it into the previous big patch, if approved.

This is okay.

Thanks, David
diff mbox

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d8529f8..5727068 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3039,7 +3039,7 @@  (define_insn_and_split "*and<mode>3_imm_dot_shifted"
 	(compare:CC
 	  (and:GPR
 	    (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
-			  (match_operand:GPR 4 "const_int_operand" "n,n"))
+			  (match_operand:SI 4 "const_int_operand" "n,n"))
 	    (match_operand:GPR 2 "const_int_operand" "n,n"))
 	  (const_int 0)))
    (clobber (match_scratch:GPR 0 "=r,r"))]
@@ -3402,7 +3402,7 @@  (define_insn "*rotl<mode>3_mask"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 		  [(match_operand:GPR 1 "gpc_reg_operand" "r")
-		   (match_operand:GPR 2 "reg_or_cint_operand" "rn")])
+		   (match_operand:SI 2 "reg_or_cint_operand" "rn")])
 		 (match_operand:GPR 3 "const_int_operand" "n")))]
   "rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
 {
@@ -3416,7 +3416,7 @@  (define_insn_and_split "*rotl<mode>3_mask_dot"
 	(compare:CC
 	  (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 		    [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
-		     (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")])
+		     (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")])
 		   (match_operand:GPR 3 "const_int_operand" "n,n"))
 	  (const_int 0)))
    (clobber (match_scratch:GPR 0 "=r,r"))]
@@ -3447,7 +3447,7 @@  (define_insn_and_split "*rotl<mode>3_mask_dot2"
 	(compare:CC
 	  (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 		    [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
-		     (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")])
+		     (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")])
 		   (match_operand:GPR 3 "const_int_operand" "n,n"))
 	  (const_int 0)))
    (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
@@ -3482,7 +3482,7 @@  (define_insn "*rotl<mode>3_insert"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(ior:GPR (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 			   [(match_operand:GPR 1 "gpc_reg_operand" "r")
-			    (match_operand:GPR 2 "const_int_operand" "n")])
+			    (match_operand:SI 2 "const_int_operand" "n")])
 			  (match_operand:GPR 3 "const_int_operand" "n"))
 		 (and:GPR (match_operand:GPR 5 "gpc_reg_operand" "0")
 			  (match_operand:GPR 6 "const_int_operand" "n"))))]
@@ -3502,7 +3502,7 @@  (define_insn "*rotl<mode>3_insert_2"
 			  (match_operand:GPR 6 "const_int_operand" "n"))
 		 (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
 			   [(match_operand:GPR 1 "gpc_reg_operand" "r")
-			    (match_operand:GPR 2 "const_int_operand" "n")])
+			    (match_operand:SI 2 "const_int_operand" "n")])
 			  (match_operand:GPR 3 "const_int_operand" "n"))))]
   "rs6000_is_valid_insert_mask (operands[3], operands[4], <MODE>mode)
    && UINTVAL (operands[3]) + UINTVAL (operands[6]) + 1 == 0"
@@ -3517,7 +3517,7 @@  (define_insn "*rotl<mode>3_insert_3"
 	(ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
 			  (match_operand:GPR 4 "const_int_operand" "n"))
 		 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-			     (match_operand:GPR 2 "const_int_operand" "n"))))]
+			     (match_operand:SI 2 "const_int_operand" "n"))))]
   "INTVAL (operands[2]) == exact_log2 (UINTVAL (operands[4]) + 1)"
 {
   if (<MODE>mode == SImode)
@@ -3532,7 +3532,7 @@  (define_insn "*rotl<mode>3_insert_4"
 	(ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
 			  (match_operand:GPR 4 "const_int_operand" "n"))
 		 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-			       (match_operand:GPR 2 "const_int_operand" "n"))))]
+			       (match_operand:SI 2 "const_int_operand" "n"))))]
   "<MODE>mode == SImode &&
    GET_MODE_PRECISION (<MODE>mode)
    == INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4]))"
@@ -3552,9 +3552,9 @@  (define_insn "*rotl<mode>3_insert_4"
 (define_split
   [(set (match_operand:GPR 0 "gpc_reg_operand")
 	(ior:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand")
-			     (match_operand:GPR 3 "const_int_operand"))
+			     (match_operand:SI 3 "const_int_operand"))
 		 (lshiftrt:GPR (match_operand:GPR 2 "gpc_reg_operand")
-			       (match_operand:GPR 4 "const_int_operand"))))]
+			       (match_operand:SI 4 "const_int_operand"))))]
   "can_create_pseudo_p ()
    && INTVAL (operands[3]) + INTVAL (operands[4])
       >= GET_MODE_PRECISION (<MODE>mode)"
@@ -3576,9 +3576,9 @@  (define_split
 (define_split
   [(set (match_operand:GPR 0 "gpc_reg_operand")
 	(ior:GPR (lshiftrt:GPR (match_operand:GPR 2 "gpc_reg_operand")
-			       (match_operand:GPR 4 "const_int_operand"))
+			       (match_operand:SI 4 "const_int_operand"))
 		 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand")
-			     (match_operand:GPR 3 "const_int_operand"))))]
+			     (match_operand:SI 3 "const_int_operand"))))]
   "can_create_pseudo_p ()
    && INTVAL (operands[3]) + INTVAL (operands[4])
       >= GET_MODE_PRECISION (<MODE>mode)"