From 9e740e7d71d02369774e1380902bddd9681c463f Mon Sep 17 00:00:00 2001
From: Oleg Endo <olegendo@gcc.gnu.org>
Date: Sun, 21 Jul 2024 14:11:21 +0900
Subject: [PATCH] SH: Fix outage caused by recently added 2nd combine pass after reg alloc
I've also confirmed on the CSiBE set that the secondary combine pass is
actually beneficial on SH. It does result in some code size reductions.
gcc/CHangeLog:
* config/sh/sh.md (mov_neg_si_t): Allow insn and split after
register allocation.
(*treg_noop_move): New insn.
---
gcc/config/sh/sh.md | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
@@ -8407,21 +8407,29 @@
{
gcc_assert (t_reg_operand (operands[1], VOIDmode));
return "subc %0,%0";
}
- "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)"
+ "&& !t_reg_operand (operands[1], VOIDmode)"
[(const_int 0)]
{
sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
if (ti.remove_trailing_nott ())
emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
DONE;
}
[(set_attr "type" "arith")])
+;; no-op T bit move which can result from other optimizations.
+(define_insn_and_split "*treg_noop_move"
+ [(set (reg:SI T_REG) (reg:SI T_REG))]
+ "TARGET_SH1"
+ "#"
+ "&& 1"
+ [(const_int 0)])
+
;; Invert the T bit.
;; On SH2A we can use the nott insn. On anything else this must be done with
;; multiple insns like:
;; movt Rn
--
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