From patchwork Fri May 31 21:28:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 248018 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id A0F092C0090 for ; Sat, 1 Jun 2013 07:28:57 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=TIHboQUtc+ezOqwXSjh BfP7lV4ehSeu6uzF3r4gTNba7Hl3eBSEqJZZSRv4OaI3fQ3h1afBBKevufek85nx NLPw1yt9qEWz7A0HHSj76WiL4HcHGGaXgF7JCTD7JZDhl6pVAnj6BttVZRNhF65u XTUHRyh3FQ/G22ZTPEchjLz8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=6CRUL633MigdH9Mgkku1hlnTT JU=; b=Tsg+pjMdknySuMGGCzpa1eeNexS2RFgeGuOCsw+fxAHbYQyO16nBcTPyJ W6uVGAxRfsgh+0e2M0lA1YHxDvI9mwZA2pwH0ATf8D04gYDGmc380ABqeqPmKx7D bbpvrDXe3GfF2760VjRxmcFTMz31NPQA3szRQBzJZvyCQ8TUQw= Received: (qmail 16937 invoked by alias); 31 May 2013 21:28:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16890 invoked by uid 89); 31 May 2013 21:28:38 -0000 X-Spam-SWARE-Status: No, score=-3.1 required=5.0 tests=AWL, BAYES_00, KHOP_THREADED, RP_MATCHES_RCVD, TW_SR autolearn=ham version=3.3.1 Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 31 May 2013 21:28:37 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id r4VLSOFF052814; Fri, 31 May 2013 14:28:24 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id r4VLSO1k052791; Fri, 31 May 2013 14:28:24 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 2/6] rs6000: dot for lshrsi3 Date: Fri, 31 May 2013 14:28:07 -0700 Message-Id: In-Reply-To: <14577e1c6b530d6f4feda94ba84896983b05513b.1370028541.git.segher@kernel.crashing.org> References: <14577e1c6b530d6f4feda94ba84896983b05513b.1370028541.git.segher@kernel.crashing.org> In-Reply-To: <14577e1c6b530d6f4feda94ba84896983b05513b.1370028541.git.segher@kernel.crashing.org> References: <14577e1c6b530d6f4feda94ba84896983b05513b.1370028541.git.segher@kernel.crashing.org> This moves lshrsi3 over and merges it with lshrdi3. The immediate version is split off since it needs a different condition (and is a separate instruction anyway). Tested as per usual; okay? 2013-05-31 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (lshrsi3): Delete. * config/rs6000/integer.mdm: (lshrdi3): Delete. (lshr3, lshr3_imm): New. * config/rs6000/integer.md: Regenerate. --- gcc/config/rs6000/integer.md | 177 +++++++++++++++++++++++++++++------------- gcc/config/rs6000/integer.mdm | 28 ++++--- gcc/config/rs6000/rs6000.md | 75 ------------------ 3 files changed, 143 insertions(+), 137 deletions(-) diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md index 0884e0f..2be1f35 100644 --- a/gcc/config/rs6000/integer.md +++ b/gcc/config/rs6000/integer.md @@ -32,90 +32,163 @@ ; slw[.], srw[.], srawi[.], sraw[.], sld[.], srd[.], sradi[.], srad[.] -(define_insn "lshrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" +(define_insn "lshr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "sr %0,%1,%2" + [(set_attr "type" "var_shift_rotate") ; var_delayed_compare +]) + +(define_insn "*lshr3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - srd %0,%1,%2 - srdi %0,%1,%H2" - [(set_attr "type" "var_shift_rotate,shift") ; var_delayed_compare,delayed_compare + sr. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate") ; var_delayed_compare +]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "(mode == Pmode && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*lshr3_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" + "@ + sr. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate") ; var_delayed_compare +]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "(mode == Pmode && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*lshr3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + "sri %0,%1,%2" + [(set_attr "type" "shift") ; delayed_compare ]) -(define_insn "*lshrdi3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") +(define_insn "*lshr3_imm_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) (const_int 0))) - (clobber (match_scratch:DI 0 "=r,r,r,r"))] - "(TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)" + (clobber (match_scratch:GPR 0 "=r,r"))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && (mode == Pmode && rs6000_gen_cell_microcode)" "@ - srd. %0,%1,%2 - srdi. %0,%1,%H2 - # + sri. %0,%1,%2 #" - [(set_attr "length" "4,4,8,8") - (set_attr "dot" "yes,yes,no,no") - (set_attr "type" "var_shift_rotate,shift,var_shift_rotate,shift") ; var_delayed_compare,delayed_compare + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "shift") ; delayed_compare ]) (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) (const_int 0))) - (clobber (match_scratch:DI 0 ""))] - "((TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)) + (clobber (match_scratch:GPR 0 ""))] + "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && (mode == Pmode && rs6000_gen_cell_microcode)) && (reload_completed)" [(set (match_dup 0) - (lshiftrt:DI (match_dup 1) - (match_dup 2))) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -(define_insn "*lshrdi3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") +(define_insn "*lshr3_imm_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (lshiftrt:DI (match_dup 1) - (match_dup 2)))] - "(TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && (mode == Pmode && rs6000_gen_cell_microcode)" "@ - srd. %0,%1,%2 - srdi. %0,%1,%H2 - # + sri. %0,%1,%2 #" - [(set_attr "length" "4,4,8,8") - (set_attr "dot" "yes,yes,no,no") - (set_attr "type" "var_shift_rotate,shift,var_shift_rotate,shift") ; var_delayed_compare,delayed_compare + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "shift") ; delayed_compare ]) (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (lshiftrt:DI (match_dup 1) - (match_dup 2)))] - "((TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && (mode == Pmode && rs6000_gen_cell_microcode)) && (reload_completed)" [(set (match_dup 0) - (lshiftrt:DI (match_dup 1) - (match_dup 2))) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] diff --git a/gcc/config/rs6000/integer.mdm b/gcc/config/rs6000/integer.mdm index 23ff8ca..7dd68dc 100644 --- a/gcc/config/rs6000/integer.mdm +++ b/gcc/config/rs6000/integer.mdm @@ -28,16 +28,24 @@ ; slw[.], srw[.], srawi[.], sraw[.], sld[.], srd[.], sradi[.], srad[.] -(define_dot_insn "lshrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" - "DImode == Pmode && rs6000_gen_cell_microcode" - "@ - srd %0,%1,%2 - srdi %0,%1,%H2" - [(set_attr "type" "var_shift_rotate,shift") ; var_delayed_compare,delayed_compare +(define_dot_insn "lshr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "mode == Pmode && rs6000_gen_cell_microcode" + "sr %0,%1,%2" + [(set_attr "type" "var_shift_rotate") ; var_delayed_compare +]) + +(define_dot_insn "*lshr3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + "mode == Pmode && rs6000_gen_cell_microcode" + "sri %0,%1,%2" + [(set_attr "type" "shift") ; delayed_compare ]) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7adde36..f28003d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4290,17 +4290,6 @@ (define_split (const_int 0)))] "") -(define_insn "lshrsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))] - "" - "@ - mr %0,%1 - srw %0,%1,%2 - srwi %0,%1,%h2" - [(set_attr "type" "integer,var_shift_rotate,shift")]) - (define_insn "*lshrsi3_64" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI @@ -4313,70 +4302,6 @@ (define_insn "*lshrsi3_64" [(set_attr "type" "var_shift_rotate,shift")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i")) - (const_int 0))) - (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))] - "TARGET_32BIT" - "@ - mr. %1,%1 - srw. %3,%1,%2 - srwi. %3,%1,%h2 - # - # - #" - [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") - (set_attr "length" "4,4,4,8,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 3) - (lshiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") - (lshiftrt:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT" - "@ - mr. %0,%1 - srw. %0,%1,%2 - srwi. %0,%1,%h2 - # - # - #" - [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") - (set_attr "length" "4,4,4,8,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (lshiftrt:SI (match_dup 1) (match_dup 2)))] - "TARGET_32BIT && reload_completed" - [(set (match_dup 0) - (lshiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i"))