diff mbox series

testcase for 2-2 combine

Message ID e20638aa732314eabc466c0d8a3a571b32ef54f6.1532966672.git.segher@kernel.crashing.org
State New
Headers show
Series testcase for 2-2 combine | expand

Commit Message

Segher Boessenkool July 30, 2018, 4:07 p.m. UTC 
Committing.


Segher


2018-07-30  Segher Boessenkool  <segher@kernel.crashing.org>

gcc/testsuite/
	PR rtl-optimization/85160
	* gcc.target/powerpc/combine-2-2.c: New testcase.

---
 gcc/testsuite/gcc.target/powerpc/combine-2-2.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/combine-2-2.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/combine-2-2.c b/gcc/testsuite/gcc.target/powerpc/combine-2-2.c
new file mode 100644
index 0000000..234476d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/combine-2-2.c
@@ -0,0 +1,17 @@ 
+/* { dg-options "-O2" } */
+
+/* PR85160 */
+
+/* Originally, the "x >> 14" are CSEd away (eventually becoming a srawi
+   instruction), and the two ANDs remain separate instructions because
+   combine cannot deal with this.
+
+   Now that combine knows how to combine two RTL insns into two, it manages
+   to make this just the sum of two rlwinm instructions.  */
+
+int f(int x)
+{
+  return ((x >> 14) & 6) + ((x >> 14) & 4);
+}
+
+/* { dg-final { scan-assembler-not {\msrawi\M} } } */