From patchwork Mon Dec 8 14:18:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 418701 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7EC971400DD for ; Tue, 9 Dec 2014 01:19:53 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=Sx6jps62wnqoG0fhdpm +LtuNp+hKhOErn+cK4i8OnReCqLRg2d4xa3f/wU4ZemOe1nBlmX0hyrjRE5xEhMq j+DX28rr1ZUCU86JL9mW7QwPQM5mKsQN6ziM10dKfnFVrZmrWoUQdCyG592bBMzZ tMDNHXPz3vE9oReKKq8bCsmk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=61t+c16CaMFxsVGBtCNOSSZfw OM=; b=N9lF1PVfma64lpqx1wvWSL2OMk9lLF9A2+JFy0ZwsMpKESVtT0ETxQPyC z39ZqCrFQCJmum98MBVYLbByvzZX6jrmCfBavUCRdfmWiokod0/7yaHZq1LwASpa kDuQd0QrKFZ+PiBUIW1M6Q7coXAAPR5sx/P6eWI0Lq2HDdkXhw= Received: (qmail 17472 invoked by alias); 8 Dec 2014 14:18:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17280 invoked by uid 89); 8 Dec 2014 14:18:25 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 08 Dec 2014 14:18:23 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id sB8EILf3032563; Mon, 8 Dec 2014 06:18:21 -0800 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id sB8EILl1032554; Mon, 8 Dec 2014 06:18:21 -0800 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 02/10] rs6000: Remove addic alternative from various lo_sum patterns Date: Mon, 8 Dec 2014 06:18:03 -0800 Message-Id: In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes This means we do not allow GPR0 as base address of those anymore. The alternative is to not allow the carry bit to be live over any lo_sum, which is more expensive. 2014-12-08 Segher Boessenkool gcc/ PR target/64180 * config/rs6000/darwin.md (macho_low_si): Remove "r" alternative. (macho_low_di): Ditto. * config/rs6000/rs6000.md (*largetoc_low): Ditto. (tocref): Ditto. (elf_low): Ditto. * config/rs6000/spe.md (mov_si_e500_subreg0_elf_low_be): Ditto. (mov_si_e500_subreg0_elf_low_le): Ditto. (mov_si_e500_subreg4_elf_low_be): Ditto. Reformat condition. (mov_si_e500_subreg4_elf_low_le): Ditto. --- gcc/config/rs6000/darwin.md | 16 ++++++---------- gcc/config/rs6000/rs6000.md | 18 +++++++----------- gcc/config/rs6000/spe.md | 18 +++++++++--------- 3 files changed, 22 insertions(+), 30 deletions(-) diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 8b816b7..764f847 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -213,22 +213,18 @@ (define_expand "macho_low" }) (define_insn "macho_low_si" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "TARGET_MACHO && ! TARGET_64BIT" - "@ - la %0,lo16(%2)(%1) - addic %0,%1,lo16(%2)") + "la %0,lo16(%2)(%1)") (define_insn "macho_low_di" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "TARGET_MACHO && TARGET_64BIT" - "@ - la %0,lo16(%2)(%1) - addic %0,%1,lo16(%2)") + "la %0,lo16(%2)(%1)") (define_split [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "") diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f3b5aae..abf20c3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -10712,13 +10712,11 @@ (define_insn "*largetoc_high_plus_aix" "addis %0,%1+%3@u(%2)") (define_insn "*largetoc_low" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") (match_operand:DI 2 "" "")))] "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" - "@ - addi %0,%1,%2@l - addic %0,%1,%2@l") + "addi %0,%1,%2@l") (define_insn "*largetoc_low_aix" [(set (match_operand:P 0 "gpc_reg_operand" "=r") @@ -10728,7 +10726,7 @@ (define_insn "*largetoc_low_aix" "la %0,%2@l(%1)") (define_insn_and_split "*tocref" - [(set (match_operand:P 0 "gpc_reg_operand" "=b*r") + [(set (match_operand:P 0 "gpc_reg_operand" "=b") (match_operand:P 1 "small_toc_ref" "R"))] "TARGET_TOC" "la %0,%a1" @@ -10747,13 +10745,11 @@ (define_insn "elf_high" "lis %0,%1@ha") (define_insn "elf_low" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "TARGET_ELF && ! TARGET_64BIT" - "@ - la %0,%2@l(%1) - addic %0,%1,%K2") + "la %0,%2@l(%1)") ;; Call and call_value insns (define_expand "call" diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 8eec7b7..07c293c 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -2519,7 +2519,7 @@ (define_insn "*mov_si_e500_subreg0_le" (define_insn_and_split "*mov_si_e500_subreg0_elf_low_be" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "WORDS_BIG_ENDIAN && (((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) @@ -2538,13 +2538,13 @@ (define_insn_and_split "*mov_si_e500_subreg0_elf_low_be" (define_insn "*mov_si_e500_subreg0_elf_low_le" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "!WORDS_BIG_ENDIAN && (((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) || (TARGET_SPE && mode != DFmode && mode != TFmode)) && TARGET_ELF && !TARGET_64BIT)" - "addic %0,%1,%K2") + "addi %0,%1,%K2") ;; ??? Could use evstwwe for memory stores in some cases, depending on ;; the offset. @@ -2592,17 +2592,17 @@ (define_insn "mov_si_e500_subreg4_le" (define_insn "*mov_si_e500_subreg4_elf_low_be" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "WORDS_BIG_ENDIAN - && (((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) - || (TARGET_SPE && mode != DFmode && mode != TFmode)) - && TARGET_ELF && !TARGET_64BIT)" - "addic %0,%1,%K2") + && ((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) + || (TARGET_SPE && mode != DFmode && mode != TFmode)) + && TARGET_ELF && !TARGET_64BIT" + "addi %0,%1,%K2") (define_insn_and_split "*mov_si_e500_subreg4_elf_low_le" [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4) - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "!WORDS_BIG_ENDIAN && (((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))