diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 665fced..d67b4e4 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5001,22 +5001,44 @@ (define_split
   "")
 
 
-(define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
+(define_expand "ashr<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+	(ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+		      (match_operand:GPR 2 "reg_or_cint_operand" "")))]
+  ""
+{
+  /* The generic code does not generate optimal code for the low word
+     (it should be a rlwimi and a rot).  Until we have target code to
+     solve this generically, keep this expander.  */
+
+  if (<MODE>mode == DImode && !TARGET_POWERPC64)
+    {
+      if (CONST_INT_P (operands[2]))
+	{
+	  emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
+	  DONE;
+	}
+      else
+	FAIL;
+    }
+})
+
+(define_insn "*ashr<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+	(ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+		      (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))]
   ""
   "@
-   sraw %0,%1,%2
-   srawi %0,%1,%h2"
+   sra<wd> %0,%1,%2
+   sra<wd>i %0,%1,%<hH>2"
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*ashrsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-  	(sign_extend:DI
+	(sign_extend:DI
 	    (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
+			 (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))]
   "TARGET_POWERPC64"
   "@
    sraw %0,%1,%2
@@ -5024,50 +5046,53 @@ (define_insn "*ashrsi3_64"
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
+(define_insn_and_split "*ashr<mode>3_dot"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+	(compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
+				  (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-  ""
+   (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
+  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
-   sraw. %3,%1,%2
-   srawi. %3,%1,%h2
+   sra<wd>. %0,%1,%2
+   sra<wd>i. %0,%1,%<hH>2
    #
    #"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(ashiftrt:GPR (match_dup 1)
+		      (match_dup 2)))
+   (set (match_dup 3)
+	(compare:CC (match_dup 0)
+		    (const_int 0)))]
+  ""
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no,yes,no")
    (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
-  [(set (match_dup 3)
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
+(define_insn_and_split "*ashr<mode>3_dot2"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
+	(compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
+				  (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  ""
+   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+	(ashiftrt:GPR (match_dup 1)
+		      (match_dup 2)))]
+  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
-   sraw. %0,%1,%2
-   srawi. %0,%1,%h2
+   sra<wd>. %0,%1,%2
+   sra<wd>i. %0,%1,%<hH>2
    #
    #"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(ashiftrt:GPR (match_dup 1)
+		      (match_dup 2)))
+   (set (match_dup 3)
+	(compare:CC (match_dup 0)
+		    (const_int 0)))]
+  ""
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no,yes,no")
    (set_attr "dot" "yes")
@@ -5112,22 +5137,6 @@ (define_expand "rsqrt<mode>2"
   DONE;
 })
 
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(ashiftrt:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-
 ;; Floating-point insns, excluding normal data motion.  We combine the SF/DF
 ;; modes here, and also add in conditional vsx/power8-vector support to access
 ;; values in the traditional Altivec registers if the appropriate
@@ -7712,99 +7721,6 @@ (define_split
 		    (const_int 0)))]
   "")
 
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		     (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_POWERPC64)
-    ;
-  else if (GET_CODE (operands[2]) == CONST_INT)
-    {
-      emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-  else
-    FAIL;
-}")
-
-(define_insn "*ashrdi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
-  "TARGET_POWERPC64"
-  "@
-   srad %0,%1,%2
-   sradi %0,%1,%H2"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no")])
-
-(define_insn "*ashrdi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-  "TARGET_64BIT"
-  "@
-   srad. %3,%1,%2
-   sradi. %3,%1,%H2
-   #
-   #"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no,yes,no")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(ashiftrt:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*ashrdi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ashiftrt:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT"
-  "@
-   srad. %0,%1,%2
-   sradi. %0,%1,%H2
-   #
-   #"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no,yes,no")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
-				 (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ashiftrt:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(ashiftrt:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
 (define_expand "anddi3"
   [(parallel
     [(set (match_operand:DI 0 "gpc_reg_operand" "")
