From patchwork Sun Jun 22 02:47:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 362504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9A2B414008F for ; Sun, 22 Jun 2014 12:52:28 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=Qh6P6adcKmzkME34cGL CtiOcCd4CL2ElHC0X5LddTkG0UOHThSX54V7a+o5Cjy/DjfULpWvLB8HNP+EklTH b7SfFzLZuXLC6UdqqVn5XW3P35l8TklH8Gi/eKq+uPRdVthubVDtZhHc4grRT/Oa Iut6iIOXUu8ZskBbnyrZmbq4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=zlwcdRdGbsPo2+JdIPD3Z1P+a lM=; b=hv5Xhcf0dt8DH/4smtEHk7CNRNBieQMfu1AXDeTibqulZ6AyE90YOPEu1 AxEBpAou15C1Vepiudwm2voqPyA3pxeFtJuM3GqTVfzbu6g6LUVWwmWfwtn8W7qu eMB1AYRcsyxt3naAMd6LhnK/q5JFR6Ndo6U0f5Z8/jcl2mbVzs= Received: (qmail 1202 invoked by alias); 22 Jun 2014 02:51:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 1002 invoked by uid 89); 22 Jun 2014 02:51:57 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sun, 22 Jun 2014 02:51:54 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s5M2mbTM033383; Sat, 21 Jun 2014 19:48:37 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s5M2mbpb033382; Sat, 21 Jun 2014 19:48:37 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 5/6] rs6000: Merge ashrsi3 and ashrdi3 Date: Sat, 21 Jun 2014 19:47:01 -0700 Message-Id: In-Reply-To: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> References: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> In-Reply-To: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> References: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> X-IsSubscribed: yes The last (and ugliest) kind of shift. Bootstrapped and tested on powerpc64-linux, {-m64,-m64/-mtune=power8, -m32,-m32/-mpowerpc64}, no regressions. Okay to apply? Segher 2014-06-21 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (ashrsi3, two anonymous define_insns and define_splits, ashrdi3, *ashrdi3_internal1, *ashrdi3_internal2 and split, *ashrdi3_internal3 and split): Delete, merge into... (ashr3): New expander. (*ashr3, ashr3_dot, ashr3_dot2): New. (*ashrsi3_64): Fix formatting. Replace "i" by "n". --- gcc/config/rs6000/rs6000.md | 210 +++++++++++++------------------------------- 1 file changed, 63 insertions(+), 147 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 665fced..d67b4e4 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5001,22 +5001,44 @@ (define_split "") -(define_insn "ashrsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] +(define_expand "ashr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:GPR 2 "reg_or_cint_operand" "")))] + "" +{ + /* The generic code does not generate optimal code for the low word + (it should be a rlwimi and a rot). Until we have target code to + solve this generically, keep this expander. */ + + if (mode == DImode && !TARGET_POWERPC64) + { + if (CONST_INT_P (operands[2])) + { + emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); + DONE; + } + else + FAIL; + } +}) + +(define_insn "*ashr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] "" "@ - sraw %0,%1,%2 - srawi %0,%1,%h2" + sra %0,%1,%2 + srai %0,%1,%2" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) (define_insn "*ashrsi3_64" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (sign_extend:DI + (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] + (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] "TARGET_POWERPC64" "@ sraw %0,%1,%2 @@ -5024,50 +5046,53 @@ (define_insn "*ashrsi3_64" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) +(define_insn_and_split "*ashr3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "" + (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - sraw. %3,%1,%2 - srawi. %3,%1,%h2 + sra. %0,%1,%2 + srai. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ashiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" +(define_insn_and_split "*ashr3_dot2" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (ashiftrt:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - sraw. %0,%1,%2 - srawi. %0,%1,%h2 + sra. %0,%1,%2 + srai. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") @@ -5112,22 +5137,6 @@ (define_expand "rsqrt2" DONE; }) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (ashiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - - ;; Floating-point insns, excluding normal data motion. We combine the SF/DF ;; modes here, and also add in conditional vsx/power8-vector support to access ;; values in the traditional Altivec registers if the appropriate @@ -7712,99 +7721,6 @@ (define_split (const_int 0)))] "") -(define_expand "ashrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")))] - "" - " -{ - if (TARGET_POWERPC64) - ; - else if (GET_CODE (operands[2]) == CONST_INT) - { - emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); - DONE; - } - else - FAIL; -}") - -(define_insn "*ashrdi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" - "@ - srad %0,%1,%2 - sradi %0,%1,%H2" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) - -(define_insn "*ashrdi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT" - "@ - srad. %3,%1,%2 - sradi. %3,%1,%H2 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ashiftrt:DI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*ashrdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - srad. %0,%1,%2 - sradi. %0,%1,%H2 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ashiftrt:DI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_expand "anddi3" [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")