From patchwork Mon Jun 13 16:28:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 1642912 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=Zo+9KB6z; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LMHNV1k6tz9s0r for ; Tue, 14 Jun 2022 02:39:52 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 368E83899047 for ; Mon, 13 Jun 2022 16:39:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 368E83899047 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655138389; bh=clyRiUMOXVvDNK0J+kiWFxc2+xE765WJkblu6GXASRg=; h=Date:Subject:To:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Zo+9KB6zzZvHHwNpiMYhVquigR0/Kcln9aLogcU5KKHRtrf7W4fdlUQEmNo9aivua WMfdV8zwH4moZAac0pz0BvPkll8EjtLjDi0RfZSKg6j2ijZxulD3h88tDoqt/coag9 wqcXVp1Z80hMsrcq+kmLCTOO44heduEHXL1JWfbc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from nh604-vm2.bullet.mail.ssk.yahoo.co.jp (nh604-vm2.bullet.mail.ssk.yahoo.co.jp [182.22.90.59]) by sourceware.org (Postfix) with SMTP id C459F383B788 for ; Mon, 13 Jun 2022 16:39:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C459F383B788 Received: from [182.22.66.104] by nh604.bullet.mail.ssk.yahoo.co.jp with NNFMP; 13 Jun 2022 16:39:23 -0000 Received: from [182.22.91.128] by t602.bullet.mail.ssk.yahoo.co.jp with NNFMP; 13 Jun 2022 16:39:22 -0000 Received: from [127.0.0.1] by omp601.mail.ssk.yahoo.co.jp with NNFMP; 13 Jun 2022 16:39:22 -0000 X-Yahoo-Newman-Property: ymail-3 X-Yahoo-Newman-Id: 935277.89519.bm@omp601.mail.ssk.yahoo.co.jp Received: (qmail 90007 invoked by alias); 13 Jun 2022 16:39:22 -0000 Received: from unknown (HELO ?192.168.2.3?) (175.177.45.189 with ) by smtp5009.mail.kks.ynwp.yahoo.co.jp with SMTP; 13 Jun 2022 16:39:22 -0000 X-YMail-JAS: 0FpFOL8VM1n0Q9NSoKA.wR.TfF4yt7D3dD6pEnLG0nh.A9XqnNEvByNlXOubfsoF2qtcoZIefV3GqaBJ.OLiMghjl4R2SrQylHTMuJALJgfcvi4FD3BB44RW5jV9VuF.NPJFedpkHQ-- X-Apparently-From: X-YMail-OSG: QUyg7VoVM1lGvaESMqcBDmneHSOuJ5CJI3fIDDPEVTZ2ZV7 oJgLAYbAI75efJu3glYSYrqSoDzxyF4_qWQI_b_32HoUhjbhmGhlalksrVnj 4rLE664ORN3.Lz_Y.BuqjXChzqQA_N_QRLGxwf.W7Yh2xKhCsBmKzS_.Ivw4 f8Giykq.P6SExpcA.Ajkg8eG95ohQrUvYqnRYaDy75peUvX43bcAKM4dYApf bzQqbUy2SnAjNALsZkSBdWBQanPgRlTH18V1bJHndEE9htCuZNeZ6s0RO9ib 4PKJGsjeObpMyA9RcqqWnq0iECY9CWRqk2ohylPB.aXDmJrYL4yiwQWgUbs1 ZExHbRItbEI1R5Jqf0OgLwdm2.IHzGG0LZOzaL1OQ0ZakHoggdN4vmChAihI iexh6nhEpRZsAIAc8LnWUF6bp8uSZx1q2IPITqw_4v.JGzEA3oT3w2Vy6TBH eq0L.HaoHFXe3lXMYD0wApeo8LbkNJsDQ1iPM1EWCOMCv9.NZoI0NHtNv0SQ iXGMqm_sG1WrGqOJbFCjM.9k_boezxpw0Gd9_gu_PM3dyC_uUBq255lcNYA4 y9SW7M9KCGGd4r0g2G2bd8_y7koDYN5uOxeC.tIG5zxjz_9267As1uhFKfJv vXbGgebpWHRjlis0Xf9693LoQZW2NLmxuEnybZwVQeV.E41XX4eOd3dvgI_V TvEVpVg4GvKFnbVssVAN2eg3vSZg7ibLGHUvfM84hiEGyVh4sgp6GuhJbezs TTGqYrJ6l4iQa9yvzcOMqzCtNmI_zNE4Y8SOo17Mq4GJWUqurapO1Gsd5uUG ZdPB2fc5zJVEKeDXyY.qfUPJ0PkC6Ior_MM4Vwm6bxoo3ZhgJ5Om5JQdanNE Wd8o59eomkcOM24719JdyvjHygvIBw07tsBkUKyi8mneMX3s8y7ToMQ_kpjz gdVA19HSBI0gs_sJE2Q-- Message-ID: Date: Tue, 14 Jun 2022 01:28:43 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: [PATCH v2 4/4] xtensa: Optimize bitwise AND operation with some specific forms of constants To: Max Filippov References: Content-Language: en-US In-Reply-To: X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Cc: GCC Patches Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" On 2022/06/13 12:49, Max Filippov wrote: > Hi Suwa-san, hi! > This change produces a bunch of regression test failures in big-endian > configuration: bad news X( that point is what i was a little worried about... > E.g. for the test gcc.c-torture/execute/struct-ini-2.c > the following assembly code is generated now: > and the following code was generated before this change: - .literal .LC1, -4096 - l32r a10, .LC1 - and a10, a8, a10 + extui a10, a8, 16, 4 // wrong! must be 12, 4 + slli a10, a10, 12 and of course, '(zero_extract)' is endianness-sensitive. (ref. 14.11 Bit-Fields, gcc-internals) the all patches that i previouly posted do not match or emit '(zero_extract)', except for this case. === This patch offers several insn-and-split patterns for bitwise AND with register and constant that can be represented as: i. 1's least significant N bits and the others 0's (17 <= N <= 31) ii. 1's most significant N bits and the others 0's (12 <= N <= 31) iii. M 1's sequence of bits and trailing N 0's bits, that cannot fit into a "MOVI Ax, simm12" instruction (1 <= M <= 16, 1 <= N <= 30) And also offers shortcuts for conditional branch if each of the abovementioned operations is (not) equal to zero. gcc/ChangeLog: * config/xtensa/predicates.md (shifted_mask_operand): New predicate. * config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one): New insn-and-split pattern. (*andsi3_const_negative_pow2, *andsi3_const_shifted_mask, *masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2, *masktrue_const_shifted_mask): Ditto. --- gcc/config/xtensa/predicates.md | 10 ++ gcc/config/xtensa/xtensa.md | 179 ++++++++++++++++++++++++++++++++ 2 files changed, 189 insertions(+) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index bcc83ada0ae..d63a6cf034c 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -52,6 +52,16 @@ (match_test "xtensa_mask_immediate (INTVAL (op))")) (match_operand 0 "register_operand"))) +(define_predicate "shifted_mask_operand" + (match_code "const_int") +{ + HOST_WIDE_INT mask = INTVAL (op); + int shift = ctz_hwi (mask); + + return IN_RANGE (shift, 1, 31) + && xtensa_mask_immediate ((uint32_t)mask >> shift); +}) + (define_predicate "extui_fldsz_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index a4477e2207e..5d0f346b01a 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -645,6 +645,83 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) +(define_insn_and_split "*andsi3_const_pow2_minus_one" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "IN_RANGE (exact_log2 (INTVAL (operands[2]) + 1), 17, 31)" + "#" + "&& 1" + [(set (match_dup 0) + (ashift:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (lshiftrt:SI (match_dup 0) + (match_dup 2)))] +{ + operands[2] = GEN_INT (32 - floor_log2 (INTVAL (operands[2]) + 1)); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && INTVAL (operands[2]) == 0x7FFFFFFF") + (const_int 5) + (const_int 6)))]) + +(define_insn_and_split "*andsi3_const_negative_pow2" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "IN_RANGE (exact_log2 (-INTVAL (operands[2])), 12, 31)" + "#" + "&& 1" + [(set (match_dup 0) + (lshiftrt:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 2)))] +{ + operands[2] = GEN_INT (floor_log2 (-INTVAL (operands[2]))); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*andsi3_const_shifted_mask" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "shifted_mask_operand" "i")))] + "! xtensa_simm12b (INTVAL (operands[2]))" + "#" + "&& 1" + [(set (match_dup 0) + (zero_extract:SI (match_dup 1) + (match_dup 3) + (match_dup 4))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 2)))] +{ + HOST_WIDE_INT mask = INTVAL (operands[2]); + int shift = ctz_hwi (mask); + int mask_size = floor_log2 (((uint32_t)mask >> shift) + 1); + int mask_pos = shift; + if (BITS_BIG_ENDIAN) + mask_pos = (32 - (mask_size + shift)) & 0x1f; + operands[2] = GEN_INT (shift); + operands[3] = GEN_INT (mask_size); + operands[4] = GEN_INT (mask_pos); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && ctz_hwi (INTVAL (operands[2])) == 1") + (const_int 5) + (const_int 6)))]) + (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=a") (ior:SI (match_operand:SI 1 "register_operand" "%r") @@ -1649,6 +1726,108 @@ (set_attr "mode" "none") (set_attr "length" "3")]) +(define_insn_and_split "*masktrue_const_pow2_minus_one" + [(set (pc) + (if_then_else (match_operator 3 "boolean_operator" + [(and:SI (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "const_int_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "IN_RANGE (exact_log2 (INTVAL (operands[1]) + 1), 17, 31)" + "#" + "&& can_create_pseudo_p ()" + [(set (match_dup 4) + (ashift:SI (match_dup 0) + (match_dup 1))) + (set (pc) + (if_then_else (match_op_dup 3 + [(match_dup 4) + (const_int 0)]) + (label_ref (match_dup 2)) + (pc)))] +{ + operands[1] = GEN_INT (32 - floor_log2 (INTVAL (operands[1]) + 1)); + operands[4] = gen_reg_rtx (SImode); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && INTVAL (operands[1]) == 0x7FFFFFFF") + (const_int 5) + (const_int 6)))]) + +(define_insn_and_split "*masktrue_const_negative_pow2" + [(set (pc) + (if_then_else (match_operator 3 "boolean_operator" + [(and:SI (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "const_int_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "IN_RANGE (exact_log2 (-INTVAL (operands[1])), 12, 30)" + "#" + "&& can_create_pseudo_p ()" + [(set (match_dup 4) + (lshiftrt:SI (match_dup 0) + (match_dup 1))) + (set (pc) + (if_then_else (match_op_dup 3 + [(match_dup 4) + (const_int 0)]) + (label_ref (match_dup 2)) + (pc)))] +{ + operands[1] = GEN_INT (floor_log2 (-INTVAL (operands[1]))); + operands[4] = gen_reg_rtx (SImode); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "6")]) + +(define_insn_and_split "*masktrue_const_shifted_mask" + [(set (pc) + (if_then_else (match_operator 4 "boolean_operator" + [(and:SI (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "shifted_mask_operand" "i")) + (match_operand:SI 2 "const_int_operand" "i")]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "(INTVAL (operands[2]) & ((1 << ctz_hwi (INTVAL (operands[1]))) - 1)) == 0 + && xtensa_b4const_or_zero ((uint32_t)INTVAL (operands[2]) >> ctz_hwi (INTVAL (operands[1])))" + "#" + "&& can_create_pseudo_p ()" + [(set (match_dup 6) + (zero_extract:SI (match_dup 0) + (match_dup 5) + (match_dup 1))) + (set (pc) + (if_then_else (match_op_dup 4 + [(match_dup 6) + (match_dup 2)]) + (label_ref (match_dup 3)) + (pc)))] +{ + HOST_WIDE_INT mask = INTVAL (operands[1]); + int shift = ctz_hwi (mask); + int mask_size = floor_log2 (((uint32_t)mask >> shift) + 1); + int mask_pos = shift; + if (BITS_BIG_ENDIAN) + mask_pos = (32 - (mask_size + shift)) & 0x1f; + operands[1] = GEN_INT (mask_pos); + operands[2] = GEN_INT ((uint32_t)INTVAL (operands[2]) >> shift); + operands[5] = GEN_INT (mask_size); + operands[6] = gen_reg_rtx (SImode); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && (uint32_t)INTVAL (operands[2]) >> ctz_hwi (INTVAL (operands[1])) == 0") + (const_int 5) + (const_int 6)))]) + ;; Zero-overhead looping support.