diff mbox series

[v2,4/4] xtensa: Optimize bitwise AND operation with some specific forms of constants

Message ID d499a2fb-8f4e-e751-af6c-d4eb67c9133f@yahoo.co.jp
State New
Headers show
Series [v2,1/4] xtensa: Improve shift operations more | expand

Commit Message

Takayuki 'January June' Suwa June 13, 2022, 4:28 p.m. UTC 
On 2022/06/13 12:49, Max Filippov wrote:
> Hi Suwa-san,
hi!

> This change produces a bunch of regression test failures in big-endian
> configuration:
bad news X(
that point is what i was a little worried about...

> E.g. for the test gcc.c-torture/execute/struct-ini-2.c
> the following assembly code is generated now:
> and the following code was generated before this change:
-	.literal .LC1, -4096
-	l32r	a10, .LC1
-	and	a10, a8, a10
+	extui	a10, a8, 16, 4  // wrong! must be 12, 4
+	slli	a10, a10, 12
and of course, '(zero_extract)' is endianness-sensitive.
(ref. 14.11 Bit-Fields, gcc-internals)

the all patches that i previouly posted do not match or emit '(zero_extract)', except for this case.

===
This patch offers several insn-and-split patterns for bitwise AND with
register and constant that can be represented as:

i.   1's least significant N bits and the others 0's (17 <= N <= 31)
ii.  1's most significant N bits and the others 0's (12 <= N <= 31)
iii. M 1's sequence of bits and trailing N 0's bits, that cannot fit into a
	"MOVI Ax, simm12" instruction (1 <= M <= 16, 1 <= N <= 30)

And also offers shortcuts for conditional branch if each of the abovementioned
operations is (not) equal to zero.

gcc/ChangeLog:

	* config/xtensa/predicates.md (shifted_mask_operand):
	New predicate.
	* config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one):
	New insn-and-split pattern.
	(*andsi3_const_negative_pow2, *andsi3_const_shifted_mask,
	*masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2,
	*masktrue_const_shifted_mask): Ditto.
---
 gcc/config/xtensa/predicates.md |  10 ++
 gcc/config/xtensa/xtensa.md     | 179 ++++++++++++++++++++++++++++++++
 2 files changed, 189 insertions(+)

Comments

Max Filippov June 14, 2022, 12:33 a.m. UTC | #1 
On Mon, Jun 13, 2022 at 9:39 AM Takayuki 'January June' Suwa
<jjsuwa_sys3175@yahoo.co.jp> wrote:
>
> On 2022/06/13 12:49, Max Filippov wrote:
> > Hi Suwa-san,
> hi!
>
> > This change produces a bunch of regression test failures in big-endian
> > configuration:
> bad news X(
> that point is what i was a little worried about...
>
> > E.g. for the test gcc.c-torture/execute/struct-ini-2.c
> > the following assembly code is generated now:
> > and the following code was generated before this change:
> -       .literal .LC1, -4096
> -       l32r    a10, .LC1
> -       and     a10, a8, a10
> +       extui   a10, a8, 16, 4  // wrong! must be 12, 4
> +       slli    a10, a10, 12
> and of course, '(zero_extract)' is endianness-sensitive.
> (ref. 14.11 Bit-Fields, gcc-internals)
>
> the all patches that i previouly posted do not match or emit '(zero_extract)', except for this case.
>
> ===
> This patch offers several insn-and-split patterns for bitwise AND with
> register and constant that can be represented as:
>
> i.   1's least significant N bits and the others 0's (17 <= N <= 31)
> ii.  1's most significant N bits and the others 0's (12 <= N <= 31)
> iii. M 1's sequence of bits and trailing N 0's bits, that cannot fit into a
>         "MOVI Ax, simm12" instruction (1 <= M <= 16, 1 <= N <= 30)
>
> And also offers shortcuts for conditional branch if each of the abovementioned
> operations is (not) equal to zero.
>
> gcc/ChangeLog:
>
>         * config/xtensa/predicates.md (shifted_mask_operand):
>         New predicate.
>         * config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one):
>         New insn-and-split pattern.
>         (*andsi3_const_negative_pow2, *andsi3_const_shifted_mask,
>         *masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2,
>         *masktrue_const_shifted_mask): Ditto.
> ---
>  gcc/config/xtensa/predicates.md |  10 ++
>  gcc/config/xtensa/xtensa.md     | 179 ++++++++++++++++++++++++++++++++
>  2 files changed, 189 insertions(+)

Regtested for target=xtensa-linux-uclibc, no new regressions.
Committed to master.
diff mbox series

Patch

diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index bcc83ada0ae..d63a6cf034c 100644
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -52,6 +52,16 @@ 
 	    (match_test "xtensa_mask_immediate (INTVAL (op))"))
        (match_operand 0 "register_operand")))
 
+(define_predicate "shifted_mask_operand"
+  (match_code "const_int")
+{
+  HOST_WIDE_INT mask = INTVAL (op);
+  int shift = ctz_hwi (mask);
+
+  return IN_RANGE (shift, 1, 31)
+	 && xtensa_mask_immediate ((uint32_t)mask >> shift);
+})
+
 (define_predicate "extui_fldsz_operand"
   (and (match_code "const_int")
        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index a4477e2207e..5d0f346b01a 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -645,6 +645,83 @@ 
    (set_attr "mode"	"SI")
    (set_attr "length"	"6")])
 
+(define_insn_and_split "*andsi3_const_pow2_minus_one"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(and:SI (match_operand:SI 1 "register_operand" "r")
+		(match_operand:SI 2 "const_int_operand" "i")))]
+  "IN_RANGE (exact_log2 (INTVAL (operands[2]) + 1), 17, 31)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(ashift:SI (match_dup 1)
+		   (match_dup 2)))
+   (set (match_dup 0)
+	(lshiftrt:SI (match_dup 0)
+		     (match_dup 2)))]
+{
+  operands[2] = GEN_INT (32 - floor_log2 (INTVAL (operands[2]) + 1));
+}
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set (attr "length")
+	(if_then_else (match_test "TARGET_DENSITY
+				   && INTVAL (operands[2]) == 0x7FFFFFFF")
+		      (const_int 5)
+		      (const_int 6)))])
+
+(define_insn_and_split "*andsi3_const_negative_pow2"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(and:SI (match_operand:SI 1 "register_operand" "r")
+		(match_operand:SI 2 "const_int_operand" "i")))]
+  "IN_RANGE (exact_log2 (-INTVAL (operands[2])), 12, 31)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(lshiftrt:SI (match_dup 1)
+		     (match_dup 2)))
+   (set (match_dup 0)
+	(ashift:SI (match_dup 0)
+		   (match_dup 2)))]
+{
+  operands[2] = GEN_INT (floor_log2 (-INTVAL (operands[2])));
+}
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"6")])
+
+(define_insn_and_split "*andsi3_const_shifted_mask"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(and:SI (match_operand:SI 1 "register_operand" "r")
+		(match_operand:SI 2 "shifted_mask_operand" "i")))]
+  "! xtensa_simm12b (INTVAL (operands[2]))"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(zero_extract:SI (match_dup 1)
+			 (match_dup 3)
+			 (match_dup 4)))
+   (set (match_dup 0)
+	(ashift:SI (match_dup 0)
+		   (match_dup 2)))]
+{
+  HOST_WIDE_INT mask = INTVAL (operands[2]);
+  int shift = ctz_hwi (mask);
+  int mask_size = floor_log2 (((uint32_t)mask >> shift) + 1);
+  int mask_pos = shift;
+  if (BITS_BIG_ENDIAN)
+    mask_pos = (32 - (mask_size + shift)) & 0x1f;
+  operands[2] = GEN_INT (shift);
+  operands[3] = GEN_INT (mask_size);
+  operands[4] = GEN_INT (mask_pos);
+}
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set (attr "length")
+	(if_then_else (match_test "TARGET_DENSITY
+				   && ctz_hwi (INTVAL (operands[2])) == 1")
+		      (const_int 5)
+		      (const_int 6)))])
+
 (define_insn "iorsi3"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(ior:SI (match_operand:SI 1 "register_operand" "%r")
@@ -1649,6 +1726,108 @@ 
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
 
+(define_insn_and_split "*masktrue_const_pow2_minus_one"
+  [(set (pc)
+	(if_then_else (match_operator 3 "boolean_operator"
+			[(and:SI (match_operand:SI 0 "register_operand" "r")
+				 (match_operand:SI 1 "const_int_operand" "i"))
+			 (const_int 0)])
+		      (label_ref (match_operand 2 "" ""))
+		      (pc)))]
+  "IN_RANGE (exact_log2 (INTVAL (operands[1]) + 1), 17, 31)"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(set (match_dup 4)
+	(ashift:SI (match_dup 0)
+		   (match_dup 1)))
+   (set (pc)
+	(if_then_else (match_op_dup 3
+			[(match_dup 4)
+			 (const_int 0)])
+		      (label_ref (match_dup 2))
+		      (pc)))]
+{
+  operands[1] = GEN_INT (32 - floor_log2 (INTVAL (operands[1]) + 1));
+  operands[4] = gen_reg_rtx (SImode);
+}
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set (attr "length")
+	(if_then_else (match_test "TARGET_DENSITY
+				   && INTVAL (operands[1]) == 0x7FFFFFFF")
+		      (const_int 5)
+		      (const_int 6)))])
+
+(define_insn_and_split "*masktrue_const_negative_pow2"
+  [(set (pc)
+	(if_then_else (match_operator 3 "boolean_operator"
+			[(and:SI (match_operand:SI 0 "register_operand" "r")
+				 (match_operand:SI 1 "const_int_operand" "i"))
+			 (const_int 0)])
+		      (label_ref (match_operand 2 "" ""))
+		      (pc)))]
+  "IN_RANGE (exact_log2 (-INTVAL (operands[1])), 12, 30)"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(set (match_dup 4)
+	(lshiftrt:SI (match_dup 0)
+		     (match_dup 1)))
+   (set (pc)
+	(if_then_else (match_op_dup 3
+			[(match_dup 4)
+			 (const_int 0)])
+		      (label_ref (match_dup 2))
+		      (pc)))]
+{
+  operands[1] = GEN_INT (floor_log2 (-INTVAL (operands[1])));
+  operands[4] = gen_reg_rtx (SImode);
+}
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"6")])
+
+(define_insn_and_split "*masktrue_const_shifted_mask"
+  [(set (pc)
+	(if_then_else (match_operator 4 "boolean_operator"
+			[(and:SI (match_operand:SI 0 "register_operand" "r")
+				 (match_operand:SI 1 "shifted_mask_operand" "i"))
+			 (match_operand:SI 2 "const_int_operand" "i")])
+		      (label_ref (match_operand 3 "" ""))
+		      (pc)))]
+  "(INTVAL (operands[2]) & ((1 << ctz_hwi (INTVAL (operands[1]))) - 1)) == 0
+   && xtensa_b4const_or_zero ((uint32_t)INTVAL (operands[2]) >> ctz_hwi (INTVAL (operands[1])))"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(set (match_dup 6)
+	(zero_extract:SI (match_dup 0)
+			 (match_dup 5)
+			 (match_dup 1)))
+   (set (pc)
+	(if_then_else (match_op_dup 4
+			[(match_dup 6)
+			 (match_dup 2)])
+		      (label_ref (match_dup 3))
+		      (pc)))]
+{
+  HOST_WIDE_INT mask = INTVAL (operands[1]);
+  int shift = ctz_hwi (mask);
+  int mask_size = floor_log2 (((uint32_t)mask >> shift) + 1);
+  int mask_pos = shift;
+  if (BITS_BIG_ENDIAN)
+    mask_pos = (32 - (mask_size + shift)) & 0x1f;
+  operands[1] = GEN_INT (mask_pos);
+  operands[2] = GEN_INT ((uint32_t)INTVAL (operands[2]) >> shift);
+  operands[5] = GEN_INT (mask_size);
+  operands[6] = gen_reg_rtx (SImode);
+}
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set (attr "length")
+	(if_then_else (match_test "TARGET_DENSITY
+				   && (uint32_t)INTVAL (operands[2]) >> ctz_hwi (INTVAL (operands[1])) == 0")
+		      (const_int 5)
+		      (const_int 6)))])
+
 
 ;; Zero-overhead looping support.