From patchwork Sun Jun 22 02:47:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 362505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 12A0D14008F for ; Sun, 22 Jun 2014 12:52:42 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=MwxJpWbAlbBRQ4RyBgS yeGo7yuNVdhDyyy29iRZKjVVoU4SkdCSXUjjh2MPZpMUow/ss68XqK+G3fUsiaqG cQLR/iXTftCfsOvoDuXz+ohZfJDZiJII9U2oEPP3vmtj7QPvyCE3zYeagDQnwZSd hhHoodAk9RPD1aip072DWitk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=8e+XzHp4vA0qdNZI3J1JRVtLo a4=; b=kJM09qOlSqDLh0wXPpQ/RIDq1weGuQK4JdvhudWKJrhwYIYejnp2/Vfsf tDgfQe8wNmacnHOvXxIVPHv83+R7sx3rvi3z+tM+Kz1AuPwRhEHBsQCBEliJXd2k RV5AptbeAk01ANlEsKMZhqFECeRf2noOgxwtt7balUK8TG3lf8= Received: (qmail 2728 invoked by alias); 22 Jun 2014 02:52:19 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 2317 invoked by uid 89); 22 Jun 2014 02:52:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sun, 22 Jun 2014 02:52:06 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s5M2mmJb034715; Sat, 21 Jun 2014 19:48:48 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s5M2mmk2034714; Sat, 21 Jun 2014 19:48:48 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 6/6] rs6000: Merge the var_shift yes/no alternatives Date: Sat, 21 Jun 2014 19:47:02 -0700 Message-Id: In-Reply-To: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> References: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> In-Reply-To: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> References: <7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org> X-IsSubscribed: yes All instructions that are "var_shift" for some alternative have the shift amount as operands[2]. This patch introduces an attribute "maybe_var_shift". If that is set to "yes", the default value of "var_shift" is set based on the operands[2] value. With that, we can merge the var_shift yes/no cases everywhere. Do so. Also change some more "i" to "n". Bootstrapped and tested on powerpc64-linux, {-m64,-m64/-mtune=power8, -m32,-m32/-mpowerpc64}, no regressions. Okay to apply? Segher 2014-06-21 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (maybe_var_shift): New define_attr. (var_shift): Use it. (rotl3, *rotlsi3_64, *rotl3_dot, *rotl3_dot2, *rotlsi3_internal4, *rotlsi3_internal5, *rotlsi3_internal6, *rotlsi3_internal8le, *rotlsi3_internal8be, *rotlsi3_internal9le, *rotlsi3_internal9be, *rotlsi3_internal10le, *rotlsi3_internal10be, *rotlsi3_internal11le, *rotlsi3_internal11be, *rotlsi3_internal12le, *rotlsi3_internal12be, ashl3, *ashlsi3_64, *ashl3_dot, *ashl3_dot2, lshr3, *lshrsi3_64, *lshr3_dot, *lshr3_dot2, *ashr3, *ashrsi3_64, *ashr3_dot, *ashr3_dot2, *rotldi3_internal4, *rotldi3_internal5, *rotldi3_internal6, *rotldi3_internal7le, *rotldi3_internal7be, *rotldi3_internal8le, *rotldi3_internal8be, *rotldi3_internal9le, *rotldi3_internal9be, *rotldi3_internal10le, *rotldi3_internal10be, *rotldi3_internal11le, *rotldi3_internal11be, *rotldi3_internal12le, *rotldi3_internal12be, *rotldi3_internal13le, *rotldi3_internal13be, *rotldi3_internal14le, *rotldi3_internal14be, *rotldi3_internal15le, *rotldi3_internal15be): Use the new attribute. Merge register and integer alternatives. --- gcc/config/rs6000/rs6000.md | 753 +++++++++++++++++++------------------------- 1 file changed, 332 insertions(+), 421 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d67b4e4..c716bae 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -205,9 +205,20 @@ (define_attr "update" "no,yes" (const_string "yes") (const_string "no"))) +;; Is this instruction using operands[2] as shift amount, and can that be a +;; register? +;; This is used for shift insns. +(define_attr "maybe_var_shift" "no,yes" (const_string "no")) + ;; Is this instruction using a shift amount from a register? ;; This is used for shift insns. -(define_attr "var_shift" "no,yes" (const_string "no")) +(define_attr "var_shift" "no,yes" + (if_then_else (and (eq_attr "type" "shift") + (eq_attr "maybe_var_shift" "yes")) + (if_then_else (match_operand 2 "gpc_reg_operand") + (const_string "yes") + (const_string "no")) + (const_string "no"))) ;; Define floating point instruction sub-types for use with Xfpu.md (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default")) @@ -3855,39 +3866,33 @@ (define_insn "*extzvdi_internal2" (define_insn "rotl3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn")))] "" - "@ - rotl %0,%1,%2 - rotli %0,%1,%2" + "rotl%I2 %0,%1,%2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotlsi3_64" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] "TARGET_POWERPC64" - "@ - rotlw %0,%1,%2 - rotlwi %0,%1,%h2" + "rotlw%I2 %0,%1,%h2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn_and_split "*rotl3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + (clobber (match_scratch:GPR 0 "=r,r"))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - rotl. %0,%1,%2 - rotli. %0,%1,%2 - # + rotl%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -3898,23 +3903,21 @@ (define_insn_and_split "*rotl3_dot" (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn_and_split "*rotl3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (rotate:GPR (match_dup 1) (match_dup 2)))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - rotl. %0,%1,%2 - rotli. %0,%1,%2 - # + rotl%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -3925,41 +3928,37 @@ (define_insn_and_split "*rotl3_dot2" (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal4" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")) - (match_operand:SI 3 "mask_operand" "n,n")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn")) + (match_operand:SI 3 "mask_operand" "n")))] "" - "@ - rlwnm %0,%1,%2,%m3,%M3 - rlwinm %0,%1,%h2,%m3,%M3" + "rlw%I2nm %0,%1,%h2,%m3,%M3" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotlsi3_internal5" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (match_operand:SI 3 "mask_operand" "n,n,n,n")) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) - (clobber (match_scratch:SI 4 "=r,r,r,r"))] + (clobber (match_scratch:SI 4 "=r,r"))] "" "@ - rlwnm. %4,%1,%2,%m3,%M3 - rlwinm. %4,%1,%h2,%m3,%M3 - # + rlw%I2nm. %4,%1,%h2,%m3,%M3 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -3980,24 +3979,22 @@ (define_split "") (define_insn "*rotlsi3_internal6" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (match_operand:SI 3 "mask_operand" "n,n,n,n")) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" "@ - rlwnm. %0,%1,%2,%m3,%M3 - rlwinm. %0,%1,%h2,%m3,%M3 - # + rlw%I2nm. %0,%1,%h2,%m3,%M3 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") @@ -4045,42 +4042,38 @@ (define_insn "*rotlsi3_internal7be" (set_attr "type" "shift")]) (define_insn "*rotlsi3_internal8le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "!BYTES_BIG_ENDIAN" "@ - rlwnm. %3,%1,%2,0xff - rlwinm. %3,%1,%h2,0xff - # + rlw%I2nm. %3,%1,%h2,0xff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal8be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "BYTES_BIG_ENDIAN" "@ - rlwnm. %3,%1,%2,0xff - rlwinm. %3,%1,%h2,0xff - # + rlw%I2nm. %3,%1,%h2,0xff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -4119,44 +4112,40 @@ (define_split "") (define_insn "*rotlsi3_internal9le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "!BYTES_BIG_ENDIAN" "@ - rlwnm. %0,%1,%2,0xff - rlwinm. %0,%1,%h2,0xff - # + rlw%I2nm. %0,%1,%h2,0xff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal9be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))] "BYTES_BIG_ENDIAN" "@ - rlwnm. %0,%1,%2,0xff - rlwinm. %0,%1,%h2,0xff - # + rlw%I2nm. %0,%1,%h2,0xff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -4193,68 +4182,60 @@ (define_split "") (define_insn "*rotlsi3_internal10le" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))] + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))] "!BYTES_BIG_ENDIAN" - "@ - rlwnm %0,%1,%2,0xffff - rlwinm %0,%1,%h2,0xffff" + "rlw%I2nm %0,%1,%h2,0xffff" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotlsi3_internal10be" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))] + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))] "BYTES_BIG_ENDIAN" - "@ - rlwnm %0,%1,%2,0xffff - rlwinm %0,%1,%h2,0xffff" + "rlw%I2nm %0,%1,%h2,0xffff" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotlsi3_internal11le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "!BYTES_BIG_ENDIAN" "@ - rlwnm. %3,%1,%2,0xffff - rlwinm. %3,%1,%h2,0xffff - # + rlw%I2nm. %3,%1,%h2,0xffff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal11be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2)) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "BYTES_BIG_ENDIAN" "@ - rlwnm. %3,%1,%2,0xffff - rlwinm. %3,%1,%h2,0xffff - # + rlw%I2nm. %3,%1,%h2,0xffff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -4293,44 +4274,40 @@ (define_split "") (define_insn "*rotlsi3_internal12le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "!BYTES_BIG_ENDIAN" "@ - rlwnm. %0,%1,%2,0xffff - rlwinm. %0,%1,%h2,0xffff - # + rlw%I2nm. %0,%1,%h2,0xffff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotlsi3_internal12be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2)) + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2)) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))] "BYTES_BIG_ENDIAN" "@ - rlwnm. %0,%1,%2,0xffff - rlwinm. %0,%1,%h2,0xffff - # + rlw%I2nm. %0,%1,%h2,0xffff #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -4368,39 +4345,33 @@ (define_split (define_insn "ashl3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn")))] "" - "@ - sl %0,%1,%2 - sli %0,%1,%2" + "sl%I2 %0,%1,%2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*ashlsi3_64" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI - (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] "TARGET_POWERPC64" - "@ - slw %0,%1,%2 - slwi %0,%1,%h2" + "slw%I2 %0,%1,%h2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn_and_split "*ashl3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + (clobber (match_scratch:GPR 0 "=r,r"))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sl. %0,%1,%2 - sli. %0,%1,%2 - # + sl%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -4411,23 +4382,21 @@ (define_insn_and_split "*ashl3_dot" (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn_and_split "*ashl3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (ashift:GPR (match_dup 1) (match_dup 2)))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sl. %0,%1,%2 - sli. %0,%1,%2 - # + sl%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -4438,9 +4407,9 @@ (define_insn_and_split "*ashl3_dot2" (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "rlwinm" @@ -4521,39 +4490,33 @@ (define_split (define_insn "lshr3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn")))] "" - "@ - sr %0,%1,%2 - sri %0,%1,%2" + "sr%I2 %0,%1,%2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*lshrsi3_64" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] "TARGET_POWERPC64" - "@ - srw %0,%1,%2 - srwi %0,%1,%h2" + "srw%I2 %0,%1,%h2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn_and_split "*lshr3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + (clobber (match_scratch:GPR 0 "=r,r"))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sr. %0,%1,%2 - sri. %0,%1,%2 - # + sr%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -4564,23 +4527,21 @@ (define_insn_and_split "*lshr3_dot" (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn_and_split "*lshr3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (lshiftrt:GPR (match_dup 1) (match_dup 2)))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sr. %0,%1,%2 - sri. %0,%1,%2 - # + sr%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -4591,9 +4552,9 @@ (define_insn_and_split "*lshr3_dot2" (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "" @@ -5024,39 +4985,33 @@ (define_expand "ashr3" }) (define_insn "*ashr3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn")))] "" - "@ - sra %0,%1,%2 - srai %0,%1,%2" + "sra%I2 %0,%1,%2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*ashrsi3_64" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI - (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "rn"))))] "TARGET_POWERPC64" - "@ - sraw %0,%1,%2 - srawi %0,%1,%h2" + "sraw%I2 %0,%1,%h2" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn_and_split "*ashr3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + (clobber (match_scratch:GPR 0 "=r,r"))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sra. %0,%1,%2 - srai. %0,%1,%2 - # + sra%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -5067,23 +5022,21 @@ (define_insn_and_split "*ashr3_dot" (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn_and_split "*ashr3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")) (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (ashiftrt:GPR (match_dup 1) (match_dup 2)))] "mode == Pmode && rs6000_gen_cell_microcode" "@ - sra. %0,%1,%2 - srai. %0,%1,%2 - # + sra%I2. %0,%1,%2 #" "&& reload_completed" [(set (match_dup 0) @@ -5094,9 +5047,9 @@ (define_insn_and_split "*ashr3_dot2" (const_int 0)))] "" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) ;; Builtins to replace a division to generate FRE reciprocal estimate ;; instructions and the necessary fixup instructions @@ -6956,35 +6909,31 @@ (define_expand "umulditi3" }) (define_insn "*rotldi3_internal4" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) - (match_operand:DI 3 "mask64_operand" "n,n")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) + (match_operand:DI 3 "mask64_operand" "n")))] "TARGET_POWERPC64" - "@ - rldc%B3 %0,%1,%2,%S3 - rldic%B3 %0,%1,%H2,%S3" + "rld%I2c%B3 %0,%1,%H2,%S3" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal5" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (and:DI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) - (match_operand:DI 3 "mask64_operand" "n,n,n,n")) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:DI 3 "mask64_operand" "n,n")) (const_int 0))) - (clobber (match_scratch:DI 4 "=r,r,r,r"))] + (clobber (match_scratch:DI 4 "=r,r"))] "TARGET_64BIT" "@ - rldc%B3. %4,%1,%2,%S3 - rldic%B3. %4,%1,%H2,%S3 - # + rld%I2c%B3. %4,%1,%H2,%S3 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -7005,24 +6954,22 @@ (define_split "") (define_insn "*rotldi3_internal6" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:DI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) - (match_operand:DI 3 "mask64_operand" "n,n,n,n")) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) + (match_operand:DI 3 "mask64_operand" "n,n")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_64BIT" "@ - rldc%B3. %0,%1,%2,%S3 - rldic%B3. %0,%1,%H2,%S3 - # + rld%I2c%B3. %0,%1,%H2,%S3 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") @@ -7042,68 +6989,60 @@ (define_split "") (define_insn "*rotldi3_internal7le" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))] "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,56 - rldicl %0,%1,%H2,56" + "rld%I2cl %0,%1,%H2,56" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal7be" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))] "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,56 - rldicl %0,%1,%H2,56" + "rld%I2cl %0,%1,%H2,56" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal8le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,56 - rldicl. %3,%1,%H2,56 - # + rld%I2cl. %3,%1,%H2,56 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal8be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,56 - rldicl. %3,%1,%H2,56 - # + rld%I2cl. %3,%1,%H2,56 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -7142,44 +7081,40 @@ (define_split "") (define_insn "*rotldi3_internal9le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,56 - rldicl. %0,%1,%H2,56 - # + rld%I2cl. %0,%1,%H2,56 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal9be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:QI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,56 - rldicl. %0,%1,%H2,56 - # + rld%I2cl. %0,%1,%H2,56 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -7216,68 +7151,60 @@ (define_split "") (define_insn "*rotldi3_internal10le" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))] "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,48 - rldicl %0,%1,%H2,48" + "rld%I2cl %0,%1,%H2,48" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal10be" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))] "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,48 - rldicl %0,%1,%H2,48" + "rld%I2cl %0,%1,%H2,48" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal11le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,48 - rldicl. %3,%1,%H2,48 - # + rld%I2cl. %3,%1,%H2,48 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal11be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,48 - rldicl. %3,%1,%H2,48 - # + rld%I2cl. %3,%1,%H2,48 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -7316,44 +7243,40 @@ (define_split "") (define_insn "*rotldi3_internal12le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,48 - rldicl. %0,%1,%H2,48 - # + rld%I2cl. %0,%1,%H2,48 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal12be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:HI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,48 - rldicl. %0,%1,%H2,48 - # + rld%I2cl. %0,%1,%H2,48 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") @@ -7390,68 +7313,60 @@ (define_split "") (define_insn "*rotldi3_internal13le" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))] "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,32 - rldicl %0,%1,%H2,32" + "rld%I2cl %0,%1,%H2,32" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal13be" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))] + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))] "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" - "@ - rldcl %0,%1,%2,32 - rldicl %0,%1,%H2,32" + "rld%I2cl %0,%1,%H2,32" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) + (set_attr "maybe_var_shift" "yes")]) (define_insn "*rotldi3_internal14le" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,32 - rldicl. %3,%1,%H2,32 - # + rld%I2cl. %3,%1,%H2,32 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal14be" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4)) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] + (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %3,%1,%2,32 - rldicl. %3,%1,%H2,32 - # + rld%I2cl. %3,%1,%H2,32 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") @@ -7490,44 +7405,40 @@ (define_split "") (define_insn "*rotldi3_internal15le" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] "TARGET_64BIT && !BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,32 - rldicl. %0,%1,%H2,32 - # + rld%I2cl. %0,%1,%H2,32 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_insn "*rotldi3_internal15be" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:DI (subreg:SI - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4)) + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4)) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))] "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ - rldcl. %0,%1,%2,32 - rldicl. %0,%1,%H2,32 - # + rld%I2cl. %0,%1,%H2,32 #" [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") + (set_attr "maybe_var_shift" "yes") (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) + (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")