From patchwork Fri May 23 06:09:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 351738 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 78FB714007E for ; Fri, 23 May 2014 16:13:43 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=Lj+Lzx16B5VTiRfX0xC LeQXOikg+u0gYtDQHdxaWEyiWnyyRtEhu+8HgZKGkDXVB3rg2YXs/5hueeEty5/+ GLgifwJKtKx+hkSgIsyK6qVXWUIK87CoCWnM65+irQcfwCqoPlxtNh8XEjbpYoK+ +KESyTbVI6CWH1EtgxOhxLuM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=yHnhg1MXHRgGOMt9WRaYYY6vN yI=; b=dQL6a2mDv/jiE0HF9yC9I5WDRoe/UJOzHujzs8kiJ82U2qG6x3CKCLjJ3 pqr+1IUzbMEPkPoAppmjcPkKILfEtgao4LcliAfcFg7Da01xZQxoHA4p9TKwUh/S 5j8XTPZ5YI0QPyZT6vQeatPRJnZRLl2Kw+nKFiNstf5HRXp1bU= Received: (qmail 6513 invoked by alias); 23 May 2014 06:13:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6493 invoked by uid 89); 23 May 2014 06:13:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 23 May 2014 06:13:17 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s4N6A6dK052543; Thu, 22 May 2014 23:10:07 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s4N6A6cu052541; Thu, 22 May 2014 23:10:06 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 2/9] rs6000: New type attribute value "halfmul" Date: Thu, 22 May 2014 23:09:40 -0700 Message-Id: In-Reply-To: <772148b5d4435e60c32b73f3c92d28b61525b6d5.1400795768.git.segher@kernel.crashing.org> References: <772148b5d4435e60c32b73f3c92d28b61525b6d5.1400795768.git.segher@kernel.crashing.org> In-Reply-To: <772148b5d4435e60c32b73f3c92d28b61525b6d5.1400795768.git.segher@kernel.crashing.org> References: <772148b5d4435e60c32b73f3c92d28b61525b6d5.1400795768.git.segher@kernel.crashing.org> X-IsSubscribed: yes This is for the legacy integer multiply-accumulate instructions. Quite a mouthful, and "mulhw" is also a terrible name since we already have a machine instruction called exactly that. Hence "halfmul". Also fixes the titan automaton description for this. 2014-05-22 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (type): Add new value "halfmul". (*macchwc, *macchw, *macchwuc, *macchwu, *machhwc, *machhw, *machhwuc, *machhwu, *maclhwc, *maclhw, *maclhwuc, *maclhwu, *nmacchwc, *nmacchw, *nmachhwc, *nmachhw, *nmaclhwc, *nmaclhw, *mulchwc, *mulchw, *mulchwuc, *mulchwu, *mulhhwc, *mulhhw, *mulhhwuc, *mulhhwu, *mullhwc, *mullhw, *mullhwuc, *mullhwu): Use it. * config/rs6000/40x.md (ppc405-imul3): Add type halfmul. * config/rs6000/440.md (ppc440-imul2): Add type halfmul. * config/rs6000/476.md (ppc476-imul): Add type halfmul. * config/rs6000/titan.md: Delete nonsensical comment. (titan_imul): Add type imul3. (titan_mulhw): Remove type imul3; add type halfmul. --- gcc/config/rs6000/40x.md | 2 +- gcc/config/rs6000/440.md | 2 +- gcc/config/rs6000/476.md | 2 +- gcc/config/rs6000/rs6000.md | 62 ++++++++++++++++++++++----------------------- gcc/config/rs6000/titan.md | 8 ++---- 5 files changed, 36 insertions(+), 40 deletions(-) diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index ed236a4..5510767 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -73,7 +73,7 @@ (define_insn_reservation "ppc405-imul2" 3 "iu_40x*2") (define_insn_reservation "ppc405-imul3" 2 - (and (eq_attr "type" "imul3") + (and (eq_attr "type" "imul3,halfmul") (eq_attr "cpu" "ppc405")) "iu_40x") diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index 2dcc58d..df3a3b5 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -76,7 +76,7 @@ (define_insn_reservation "ppc440-imul" 3 "ppc440_issue,ppc440_i_pipe") (define_insn_reservation "ppc440-imul2" 2 - (and (eq_attr "type" "imul2,imul3") + (and (eq_attr "type" "imul2,imul3,halfmul") (eq_attr "cpu" "ppc440")) "ppc440_issue,ppc440_i_pipe") diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index 8b4e65f..acfe063 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -82,7 +82,7 @@ (define_insn_reservation "ppc476-compare" 4 ppc476_i_pipe") (define_insn_reservation "ppc476-imul" 4 - (and (eq_attr "type" "imul,imul_compare,imul2,imul3") + (and (eq_attr "type" "imul,imul_compare,imul2,imul3,halfmul") (eq_attr "cpu" "ppc476")) "ppc476_issue,\ ppc476_i_pipe") diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 667aac1..3e9686e 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -160,7 +160,7 @@ (define_c_enum "unspecv" (define_attr "type" "integer,two,three, shift,var_shift_rotate,insert_word,insert_dword, - imul,imul2,imul3,lmul,idiv,ldiv, + imul,imul2,imul3,lmul,halfmul,idiv,ldiv, exts,cntlz,popcnt,isel, load,store,fpload,fpstore,vecload,vecstore, cmp, @@ -1248,7 +1248,7 @@ (define_insn "*macchwc" (match_dup 4)))] "TARGET_MULHW" "macchw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*macchw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1260,7 +1260,7 @@ (define_insn "*macchw" (match_operand:SI 3 "gpc_reg_operand" "0")))] "TARGET_MULHW" "macchw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*macchwuc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1280,7 +1280,7 @@ (define_insn "*macchwuc" (match_dup 4)))] "TARGET_MULHW" "macchwu. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*macchwu" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1292,7 +1292,7 @@ (define_insn "*macchwu" (match_operand:SI 3 "gpc_reg_operand" "0")))] "TARGET_MULHW" "macchwu %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*machhwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1314,7 +1314,7 @@ (define_insn "*machhwc" (match_dup 4)))] "TARGET_MULHW" "machhw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*machhw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1327,7 +1327,7 @@ (define_insn "*machhw" (match_operand:SI 3 "gpc_reg_operand" "0")))] "TARGET_MULHW" "machhw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*machhwuc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1349,7 +1349,7 @@ (define_insn "*machhwuc" (match_dup 4)))] "TARGET_MULHW" "machhwu. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*machhwu" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1362,7 +1362,7 @@ (define_insn "*machhwu" (match_operand:SI 3 "gpc_reg_operand" "0")))] "TARGET_MULHW" "machhwu %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*maclhwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1380,7 +1380,7 @@ (define_insn "*maclhwc" (match_dup 4)))] "TARGET_MULHW" "maclhw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*maclhw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1391,7 +1391,7 @@ (define_insn "*maclhw" (match_operand:SI 3 "gpc_reg_operand" "0")))] "TARGET_MULHW" "maclhw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*maclhwuc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1409,7 +1409,7 @@ (define_insn "*maclhwuc" (match_dup 4)))] "TARGET_MULHW" "maclhwu. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*maclhwu" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1420,7 +1420,7 @@ (define_insn "*maclhwu" (match_operand:SI 3 "gpc_reg_operand" "0")))] "TARGET_MULHW" "maclhwu %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*nmacchwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1440,7 +1440,7 @@ (define_insn "*nmacchwc" (match_dup 1)))))] "TARGET_MULHW" "nmacchw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*nmacchw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1452,7 +1452,7 @@ (define_insn "*nmacchw" (match_operand:HI 1 "gpc_reg_operand" "r")))))] "TARGET_MULHW" "nmacchw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*nmachhwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1474,7 +1474,7 @@ (define_insn "*nmachhwc" (const_int 16)))))] "TARGET_MULHW" "nmachhw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*nmachhw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1487,7 +1487,7 @@ (define_insn "*nmachhw" (const_int 16)))))] "TARGET_MULHW" "nmachhw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*nmaclhwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1505,7 +1505,7 @@ (define_insn "*nmaclhwc" (match_dup 2)))))] "TARGET_MULHW" "nmaclhw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*nmaclhw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1516,7 +1516,7 @@ (define_insn "*nmaclhw" (match_operand:HI 2 "gpc_reg_operand" "r")))))] "TARGET_MULHW" "nmaclhw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mulchwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1534,7 +1534,7 @@ (define_insn "*mulchwc" (match_dup 1))))] "TARGET_MULHW" "mulchw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mulchw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1545,7 +1545,7 @@ (define_insn "*mulchw" (match_operand:HI 1 "gpc_reg_operand" "r"))))] "TARGET_MULHW" "mulchw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mulchwuc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1563,7 +1563,7 @@ (define_insn "*mulchwuc" (match_dup 1))))] "TARGET_MULHW" "mulchwu. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mulchwu" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1574,7 +1574,7 @@ (define_insn "*mulchwu" (match_operand:HI 1 "gpc_reg_operand" "r"))))] "TARGET_MULHW" "mulchwu %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mulhhwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1594,7 +1594,7 @@ (define_insn "*mulhhwc" (const_int 16))))] "TARGET_MULHW" "mulhhw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mulhhw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1606,7 +1606,7 @@ (define_insn "*mulhhw" (const_int 16))))] "TARGET_MULHW" "mulhhw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mulhhwuc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1626,7 +1626,7 @@ (define_insn "*mulhhwuc" (const_int 16))))] "TARGET_MULHW" "mulhhwu. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mulhhwu" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1638,7 +1638,7 @@ (define_insn "*mulhhwu" (const_int 16))))] "TARGET_MULHW" "mulhhwu %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mullhwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1654,7 +1654,7 @@ (define_insn "*mullhwc" (match_dup 2))))] "TARGET_MULHW" "mullhw. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mullhw" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1664,7 +1664,7 @@ (define_insn "*mullhw" (match_operand:HI 2 "gpc_reg_operand" "r"))))] "TARGET_MULHW" "mullhw %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mullhwuc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1680,7 +1680,7 @@ (define_insn "*mullhwuc" (match_dup 2))))] "TARGET_MULHW" "mullhwu. %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) (define_insn "*mullhwu" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1690,7 +1690,7 @@ (define_insn "*mullhwu" (match_operand:HI 2 "gpc_reg_operand" "r"))))] "TARGET_MULHW" "mullhwu %0,%1,%2" - [(set_attr "type" "imul3")]) + [(set_attr "type" "halfmul")]) ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support. (define_insn "dlmzb" diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md index 1adbee5..6bb4792 100644 --- a/gcc/config/rs6000/titan.md +++ b/gcc/config/rs6000/titan.md @@ -38,17 +38,13 @@ (define_insn_reservation "titan_fxu_adder" 1 (eq_attr "cpu" "titan")) "titan_issue,titan_fxu_sh") -;; Keep the titan_imul and titan_mulhw (half-word) rules in order, to -;; ensure the proper match: the half-word instructions are tagged as -;; imul3 only, whereas regular multiplys will always carry a imul tag. - (define_insn_reservation "titan_imul" 5 - (and (eq_attr "type" "imul,imul2,imul_compare") + (and (eq_attr "type" "imul,imul2,imul3,imul_compare") (eq_attr "cpu" "titan")) "titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb") (define_insn_reservation "titan_mulhw" 4 - (and (eq_attr "type" "imul3") + (and (eq_attr "type" "halfmul") (eq_attr "cpu" "titan")) "titan_issue,titan_fxu_sh,nothing*4,titan_fxu_wb")