diff mbox

[rs6000] Fix PR78458, LRA ICE building libgcc for powerpc-linux-gnuspe e500v2

Message ID cba86d60-f597-177c-bf6b-8fab076b06ca@vnet.ibm.com
State New
Headers show

Commit Message

Peter Bergner Nov. 23, 2016, 6:13 p.m. UTC 
PR78458 shows a problem in LRA spilling caused by HARD_REGNO_CALLER_SAVE_MODE()
returning a bogus mode (IFmode).  This patch solves the problem by just
returning MODE if MODE is wide enough to save and restore NREGS itself.

This patch passed bootstrap and regtesting on powerpc64le-linux as well
as on powerpc64-linux (testsuite run in both 32-bit and 64-bit modes).
Joseph has confirmed it fixes his ICE and gets him further in his toolchain
build (now ICEs in glibc), which he has separate patches for.

Joseph, I copied the testsuite preamble from another SPE test case.
Does it look correct to you to catch the bug?

Assuming the test case is correct, is this ok for trunk?

Peter


gcc/
	PR target/78458
	* config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Return MODE
	if it is at least NREGS wide.

gcc/testsuite/
	PR target/78458
	* gcc.target/powerpc/pr78458.c: New.

Comments

Segher Boessenkool Nov. 23, 2016, 6:33 p.m. UTC | #1 
On Wed, Nov 23, 2016 at 12:13:23PM -0600, Peter Bergner wrote:
> --- gcc/config/rs6000/rs6000.h	(revision 241976)
> +++ gcc/config/rs6000/rs6000.h	(working copy)
> @@ -1279,9 +1279,11 @@ enum data_align { align_abi, align_opt,
>     enough space to account for vectors in FP regs.  However, TFmode/TDmode
>     should not use VSX instructions to do a caller save. */
>  #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE)			\
> -  (TARGET_VSX								\
> -   && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE))		\
> -   && FP_REGNO_P (REGNO)						\
> +  (NREGS <= rs6000_hard_regno_nregs[MODE][REGNO]			\
> +   ? MODE								\

Please put parens around NREGS and that last MODE.

> --- gcc/testsuite/gcc.target/powerpc/pr78458.c	(revision 0)
> +++ gcc/testsuite/gcc.target/powerpc/pr78458.c	(working copy)
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mcpu=8548 -mspe -mabi=spe -mlra" } */
> +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */

You don't need the default arguments, FWIW.

Okay for trunk.  Thanks!


Segher
Joseph Myers Nov. 23, 2016, 6:44 p.m. UTC | #2 
On Wed, 23 Nov 2016, Peter Bergner wrote:

> Joseph, I copied the testsuite preamble from another SPE test case.
> Does it look correct to you to catch the bug?

I think the preamble is fine.

I'm running execution testing with my two SPE patches and will submit them 
if results seem reasonable (since the previous state was the build 
failing, I don't have baseline results for unmodified GCC to compare 
with).
Peter Bergner Nov. 24, 2016, 2:22 a.m. UTC | #3 
On 11/23/16 12:33 PM, Segher Boessenkool wrote:
> On Wed, Nov 23, 2016 at 12:13:23PM -0600, Peter Bergner wrote:
> Please put parens around NREGS and that last MODE.
[snip]
> You don't need the default arguments, FWIW.
>
> Okay for trunk.  Thanks!

Ok, commited as revision 242818 with your suggestions.  Thanks.

Peter
diff mbox

Patch

Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h	(revision 241976)
+++ gcc/config/rs6000/rs6000.h	(working copy)
@@ -1279,9 +1279,11 @@  enum data_align { align_abi, align_opt,
    enough space to account for vectors in FP regs.  However, TFmode/TDmode
    should not use VSX instructions to do a caller save. */
 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE)			\
-  (TARGET_VSX								\
-   && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE))		\
-   && FP_REGNO_P (REGNO)						\
+  (NREGS <= rs6000_hard_regno_nregs[MODE][REGNO]			\
+   ? MODE								\
+   : TARGET_VSX								\
+     && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE))	\
+     && FP_REGNO_P (REGNO)						\
    ? V2DFmode								\
    : TARGET_E500_DOUBLE && (MODE) == SImode				\
    ? SImode								\
Index: gcc/testsuite/gcc.target/powerpc/pr78458.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr78458.c	(revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr78458.c	(working copy)
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -mlra" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+extern void bar (void);
+long double
+pr78458 (long double p1)
+{
+  bar ();
+  asm volatile ("# clobbers" :::
+		"r14", "r15", "r16", "r17", "r18", "r19",
+		"r20", "r21", "r22", "r23", "r24", "r25",
+		"r26", "r27", "r28", "r29", "r30", "r31");
+  return p1;
+}