From patchwork Thu Jan 8 01:28:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 426466 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 51C041400D5 for ; Thu, 8 Jan 2015 12:29:17 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=Sck+avaItstE BA9H0ofJDDkWv16NH9YCMZ09cc56ZwA6o4sDU5Xk+G+Ikwa6DAKlXYY5onTTzvHz fjquUdlJNMuZUPlQltjq1u1eNGDNh5GNmJktnwGw7LznkVEqLtE+/8OJA1btRPOe DMgIehvKzWtvI9erEi6pgsLCwguE0hg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=Bpx996mIAX+YW/+NFG ftIV6NvVA=; b=A/aawYhkrXCMTk6FxeuTOf+gv2fMdyNOfmrjY5tP2UbgFshiNu 9vdHvDqOSnR6O6J10OAW8ZSPjrmPjysrySCV0tUl90PI66VJVTgjgEWAHJDYqruM Dg5WuE6gUVhF72NSfs37rUj05arRAqYwElruoRSYZ2HHfeVVKz64+5VEA= Received: (qmail 23404 invoked by alias); 8 Jan 2015 01:29:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 23391 invoked by uid 89); 8 Jan 2015 01:29:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Thu, 08 Jan 2015 01:29:04 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id t081T285041580; Wed, 7 Jan 2015 17:29:02 -0800 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id t081T0Dv041572; Wed, 7 Jan 2015 17:29:00 -0800 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH] rs6000: Add eqsi/nesi storing to a 64-bit reg (PR36557) Date: Wed, 7 Jan 2015 17:28:55 -0800 Message-Id: X-IsSubscribed: yes The compiler cannot assume that the eqsi etc. patterns write a properly extended result to a DI reg. The current way to tell it is to add an extra pattern with an extend. This patch does that. A less cumbersome method of specifying this would be nice -- maybe one where we say in the SI pattern that the result is already extended correctly as DI (both sign- and zero-extended, in this case). This partially fixes PR36557 (and is the best we can do for the test case there, we cannot assume function args are correctly extended for their type). Tested as usual; okay for mainline? Segher 2015-01-07 Segher Boessenkool gcc/ PR target/36557 * config/rs6000/rs6000.md (*eqsi3_ext, *nesi3_ext): New. --- gcc/config/rs6000/rs6000.md | 60 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3da529c..6da1a6a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -12588,6 +12588,66 @@ (define_insn_and_split "*minus_ne_" (if_then_else (match_test "operands[2] == const0_rtx") (const_string "8") (const_string "12")))]) + +(define_insn_and_split "*eqsi3_ext" + [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") + (eq:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "scc_eq_operand" "rKLI"))) + (clobber (match_scratch:SI 3 "=r")) + (clobber (match_scratch:SI 4 "=r"))] + "" + "#" + "" + [(set (match_dup 4) + (clz:SI (match_dup 3))) + (set (match_dup 0) + (zero_extend:EXTSI + (lshiftrt:SI (match_dup 4) + (const_int 5))))] +{ + operands[3] = rs6000_emit_eqne (SImode, + operands[1], operands[2], operands[3]); + + if (GET_CODE (operands[4]) == SCRATCH) + operands[4] = gen_reg_rtx (SImode); +} + [(set (attr "length") + (if_then_else (match_test "operands[2] == const0_rtx") + (const_string "8") + (const_string "12")))]) + +(define_insn_and_split "*nesi3_ext" + [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") + (ne:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "scc_eq_operand" "rKLI"))) + (clobber (match_scratch:SI 3 "=r")) + (clobber (match_scratch:SI 4 "=r")) + (clobber (match_scratch:EXTSI 5 "=r"))] + "" + "#" + "" + [(set (match_dup 4) + (clz:SI (match_dup 3))) + (set (match_dup 5) + (zero_extend:EXTSI + (lshiftrt:SI (match_dup 4) + (const_int 5)))) + (set (match_dup 0) + (xor:EXTSI (match_dup 5) + (const_int 1)))] +{ + operands[3] = rs6000_emit_eqne (SImode, + operands[1], operands[2], operands[3]); + + if (GET_CODE (operands[4]) == SCRATCH) + operands[4] = gen_reg_rtx (SImode); + if (GET_CODE (operands[5]) == SCRATCH) + operands[5] = gen_reg_rtx (mode); +} + [(set (attr "length") + (if_then_else (match_test "operands[2] == const0_rtx") + (const_string "12") + (const_string "16")))]) ;; Define both directions of branch and return. If we need a reload ;; register, we'd rather use CR0 since it is much easier to copy a