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To: segher@gcc.gnu.org, dje.gcc@gmail.com, gcc-patches@gcc.gnu.org, Will Schmidt Date: Tue, 11 Aug 2020 12:23:05 -0700 In-Reply-To: References: X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-11_15:2020-08-11, 2020-08-11 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 adultscore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 spamscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008110133 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GB_TO_NAME_FREEMAIL, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Carl Love via Gcc-patches From: Carl Love Reply-To: Carl Love Cc: cel@ibm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Segher, Will: Patch 4 adds 128-bit integer shift instruction support. Carl Love --------------------------------------------------------- Test 128-bit shifts for just the int128 type. gcc/ChangeLog 2020-08-10 Carl Love * config/rs6000/altivec.md (altivec_vslq, altivec_vsrq): Add mode VEC_I128. * config/rs6000/vector.md (VEC_I128): New mode iterator. (vashlv1ti3): Change to vashl3, mode VEC_I128. (vlshrv1ti3): Change to vlshr3, mode VEC_I128. * config/rs6000/vsx.md (UNSPEC_XXSWAPD_V1TI): Change to UNSPEC_XXSWAPD_VEC_I128. (xxswapd_v1ti): Change to xxswapd_, mode VEC_I128. gcc/testsuite/ChangeLog 2020-08-10 Carl Love gcc.target/powerpc/int_128bit-runnable.c: Add shift_right, shift_left tests. --- gcc/config/rs6000/altivec.md | 16 +++++------ gcc/config/rs6000/vector.md | 27 ++++++++++--------- gcc/config/rs6000/vsx.md | 14 +++++----- .../gcc.target/powerpc/int_128bit-runnable.c | 24 +++++++++++++++-- 4 files changed, 52 insertions(+), 29 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 2763d920828..cba39852070 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2219,10 +2219,10 @@ "vsl %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vslq" - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") - (ashift:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v") - (match_operand:V1TI 2 "vsx_register_operand" "v")))] +(define_insn "altivec_vslq_" + [(set (match_operand:VEC_I128 0 "vsx_register_operand" "=v") + (ashift:VEC_I128 (match_operand:VEC_I128 1 "vsx_register_operand" "v") + (match_operand:VEC_I128 2 "vsx_register_operand" "v")))] "TARGET_TI_VECTOR_OPS" /* Shift amount in needs to be in bits[57:63] of 128-bit operand. */ "vslq %0,%1,%2" @@ -2236,10 +2236,10 @@ "vsr %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vsrq" - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") - (lshiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v") - (match_operand:V1TI 2 "vsx_register_operand" "v")))] +(define_insn "altivec_vsrq_" + [(set (match_operand:VEC_I128 0 "vsx_register_operand" "=v") + (lshiftrt:VEC_I128 (match_operand:VEC_I128 1 "vsx_register_operand" "v") + (match_operand:VEC_I128 2 "vsx_register_operand" "v")))] "TARGET_TI_VECTOR_OPS" /* Shift amount in needs to be in bits[57:63] of 128-bit operand. */ "vsrq %0,%1,%2" diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 2deff282076..682aabc4657 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -26,6 +26,9 @@ ;; Vector int modes (define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI]) +;; 128-bit int modes +(define_mode_iterator VEC_I128 [V1TI TI]) + ;; Vector int modes for parity (define_mode_iterator VEC_IP [V8HI V4SI @@ -1635,17 +1638,17 @@ "") ;; No immediate version of this 128-bit instruction -(define_expand "vashlv1ti3" - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") - (ashift:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v") - (match_operand:V1TI 2 "vsx_register_operand" "v")))] +(define_expand "vashl3" + [(set (match_operand:VEC_I128 0 "vsx_register_operand" "=v") + (ashift:VEC_I128 (match_operand:VEC_I128 1 "vsx_register_operand") + (match_operand:VEC_I128 2 "vsx_register_operand")))] "TARGET_TI_VECTOR_OPS" { /* Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */ - rtx tmp = gen_reg_rtx (V1TImode); + rtx tmp = gen_reg_rtx (mode); emit_insn(gen_xxswapd_v1ti (tmp, operands[2])); - emit_insn(gen_altivec_vslq (operands[0], operands[1], tmp)); + emit_insn(gen_altivec_vslq_ (operands[0], operands[1], tmp)); DONE; }) @@ -1658,17 +1661,17 @@ "") ;; No immediate version of this 128-bit instruction -(define_expand "vlshrv1ti3" - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") - (lshiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v") - (match_operand:V1TI 2 "vsx_register_operand" "v")))] +(define_expand "vlshr3" + [(set (match_operand:VEC_I128 0 "vsx_register_operand" "=v") + (lshiftrt:VEC_I128 (match_operand:VEC_I128 1 "vsx_register_operand") + (match_operand:VEC_I128 2 "vsx_register_operand")))] "TARGET_TI_VECTOR_OPS" { /* Shift amount in needs to be put into bits[57:63] of 128-bit operand2. */ - rtx tmp = gen_reg_rtx (V1TImode); + rtx tmp = gen_reg_rtx (mode); emit_insn(gen_xxswapd_v1ti (tmp, operands[2])); - emit_insn(gen_altivec_vsrq (operands[0], operands[1], tmp)); + emit_insn(gen_altivec_vsrq_ (operands[0], operands[1], tmp)); DONE; }) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 998af3908ad..5be535808b3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -367,7 +367,7 @@ UNSPEC_INSERTR UNSPEC_REPLACE_ELT UNSPEC_REPLACE_UN - UNSPEC_XXSWAPD_V1TI + UNSPEC_XXSWAPD_VEC_I128 ]) (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16 @@ -3144,12 +3144,12 @@ "xxpermdi %x0,%x1,%x1,2" [(set_attr "type" "vecperm")]) -;; Swap upper/lower 64-bit values in a 128-bit vector -(define_insn "xxswapd_v1ti" - [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") - (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v") - (parallel [(const_int 0)(const_int 1)])] - UNSPEC_XXSWAPD_V1TI))] +;; Swap upper/lower 64-bit values in V1TI or TI type +(define_insn "xxswapd_" + [(set (match_operand:VEC_I128 0 "vsx_register_operand" "=v") + (unspec:VEC_I128 [(match_operand:VEC_I128 1 "vsx_register_operand" "v") + (parallel [(const_int 0)(const_int 1)])] + UNSPEC_XXSWAPD_VEC_I128))] "TARGET_POWER10" ;; AIX does not support extended mnemonic xxswapd. Use the basic ;; mnemonic xxpermdi instead. diff --git a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c index d1e69cea021..b074d83bd68 100644 --- a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c @@ -53,6 +53,18 @@ void print_i128(__int128_t val) void abort (void); +__attribute__((noinline)) +__int128_t shift_right (__int128_t a, __uint128_t b) +{ + return a >> b; +} + +__attribute__((noinline)) +__int128_t shift_left (__int128_t a, __uint128_t b) +{ + return a << b; +} + int main () { int i, result_int; @@ -141,10 +153,12 @@ int main () #endif } - arg1 = 3; + // arg1 = 3; + arg1 = vec_result[0]; uarg2 = 4; expected_result = arg1*16; + // result = shift_left(arg1, uarg2); result = arg1 << uarg2; if (result != expected_result) { @@ -225,10 +239,16 @@ int main () #endif } - arg1 = 48; + // arg1 = 48; + + // use the previous result to try and keep gcc from doing the shift + // at compile time + arg1 = vec_uresult[0]; uarg2 = 4; expected_result = arg1/16; + //Not getting 128-bit shift inst generated + // result = shift_right (arg1, uarg2); result = arg1 >> uarg2; if (result != expected_result) {