| Message ID | b19b8ffe-16ea-522f-ebd8-d9041972353e@yahoo.co.jp |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] xtensa: Eliminate unnecessary general-purpose reg-reg moves | expand |
Hi Suwa-san, On Wed, Jan 18, 2023 at 9:06 PM Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> wrote: > > Register-register move instructions that can be easily seen as > unnecessary by the human eye may remain in the compiled result. > For example: > > /* example */ > double test(double a, double b) { > return __builtin_copysign(a, b); > } > > test: > add.n a3, a3, a3 > extui a5, a5, 31, 1 > ssai 1 > ;; be in the same BB > src a7, a5, a3 ;; No '0' in the source constraints > ;; No CALL insns in this span > ;; Both A3 and A7 are irrelevant to > ;; insns in this span > mov.n a3, a7 ;; An unnecessary reg-reg move > ;; A7 is not used after this > ret.n > > The last two instructions above, excluding the return instruction, > could be done like this: > > src a3, a5, a3 > > This symptom often occurs when handling DI/DFmode values with SImode > instructions. This patch solves the above problem using peephole2 > pattern. > > gcc/ChangeLog: > > * config/xtensa/xtensa.md: New peephole2 pattern that eliminates > the occurrence of general-purpose register used only once and for > transferring intermediate value. > --- > gcc/config/xtensa/xtensa.md | 45 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) With this change I see the following ICEs: in the libgcc build: gcc/libgcc/libgcov-interface.c: In function ‘__gcov_execl’: gcc/libgcc/libgcov-interface.c:228:1: error: insn does not satisfy its constraints: 228 | } | ^ (insn 96 95 98 11 (set (reg/f:SI 1 sp) (minus:SI (reg/f:SI 1 sp) (reg:SI 8 a8 [85]))) "gcc/libgcc/libgcov-interface.c":218:20 4 {subsi3} (expr_list:REG_DEAD (reg:SI 8 a8 [85]) (nil))) during RTL pass: cprop_hardreg -------------------- in the linux kernel build: linux/lib/find_bit.c: In function ‘_find_next_bit’: linux/lib/find_bit.c:70:1: error: unrecognizable insn: 70 | } | ^ (insn 74 72 75 16 (set (reg:SI 10 a10) (asm_operands:SI ("ssai 8 srli %0, %1, 16 src %0, %0, %1 src %0, %0, %0 src %0, %1, %0 ") ("=&a") 0 [ (reg/v:SI 10 a10 [orig:59 res ] [59]) ] [ (asm_input:SI ("a") linux/arch/xtensa/include/uapi/asm/swab.h:24) ] [] linux/arch/xtensa/include/uapi/asm/swab.h:24)) "linux/arch/xtensa/include/uapi/asm/swab.h":24:5 -1 (nil)) during RTL pass: cprop_hardreg linux/lib/find_bit.c:70:1: internal compiler error: in extract_constrain_insn, at recog.cc:2692 0x6c3214 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*) gcc/gcc/rtl-error.cc:108 0x6c3297 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*) gcc/gcc/rtl-error.cc:116 0x6b4735 extract_constrain_insn(rtx_insn*) gcc/gcc/recog.cc:2692 0xe1f67e copyprop_hardreg_forward_1 gcc/gcc/regcprop.cc:826 0xe20a0f execute gcc/gcc/regcprop.cc:1408
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index abcab231d8e..517dcecf2c1 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -3110,3 +3110,48 @@ FALLTHRU:; df_insn_rescan (insnR); set_insn_deleted (insnP); }) + +(define_peephole2 + [(set (match_operand 0 "register_operand") + (match_operand 1 "register_operand"))] + "GET_MODE_SIZE (GET_MODE (operands[0])) == 4 + && GET_MODE_SIZE (GET_MODE (operands[1])) == 4 + && GP_REG_P (REGNO (operands[0])) && GP_REG_P (REGNO (operands[1])) + && peep2_reg_dead_p (1, operands[1])" + [(const_int 0)] +{ + basic_block bb = BLOCK_FOR_INSN (curr_insn); + rtx_insn *head = BB_HEAD (bb), *insn; + rtx dest = operands[0], src = operands[1], pattern, t_dest; + int i; + for (insn = PREV_INSN (curr_insn); + insn && insn != head; + insn = PREV_INSN (insn)) + if (CALL_P (insn)) + break; + else if (INSN_P (insn)) + { + if (GET_CODE (pattern = PATTERN (insn)) == SET + && REG_P (t_dest = SET_DEST (pattern)) + && GET_MODE_SIZE (GET_MODE (t_dest)) == 4 + && REGNO (t_dest) == REGNO (src)) + { + extract_constrain_insn (insn); + for (i = 1; i < recog_data.n_operands; ++i) + if (strchr (recog_data.constraints[i], '0')) + goto ABORT; + SET_DEST (pattern) = gen_rtx_REG (GET_MODE (t_dest), + REGNO (dest)); + df_insn_rescan (insn); + goto FALLTHRU; + } + if (reg_overlap_mentioned_p (dest, pattern) + || reg_overlap_mentioned_p (src, pattern) + || set_of (dest, insn) + || set_of (src, insn)) + break; + } +ABORT: + FAIL; +FALLTHRU:; +})
Register-register move instructions that can be easily seen as unnecessary by the human eye may remain in the compiled result. For example: /* example */ double test(double a, double b) { return __builtin_copysign(a, b); } test: add.n a3, a3, a3 extui a5, a5, 31, 1 ssai 1 ;; be in the same BB src a7, a5, a3 ;; No '0' in the source constraints ;; No CALL insns in this span ;; Both A3 and A7 are irrelevant to ;; insns in this span mov.n a3, a7 ;; An unnecessary reg-reg move ;; A7 is not used after this ret.n The last two instructions above, excluding the return instruction, could be done like this: src a3, a5, a3 This symptom often occurs when handling DI/DFmode values with SImode instructions. This patch solves the above problem using peephole2 pattern. gcc/ChangeLog: * config/xtensa/xtensa.md: New peephole2 pattern that eliminates the occurrence of general-purpose register used only once and for transferring intermediate value. --- gcc/config/xtensa/xtensa.md | 45 +++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)