From patchwork Wed Jan 24 11:16:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 1890197 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=embecosm.com header.i=@embecosm.com header.a=rsa-sha256 header.s=google header.b=cisrlVv3; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TKhKJ3VGGz23f0 for ; Wed, 24 Jan 2024 22:18:28 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2D8C83857732 for ; Wed, 24 Jan 2024 11:18:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id 8FD18385E453 for ; Wed, 24 Jan 2024 11:16:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8FD18385E453 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8FD18385E453 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::534 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706095018; cv=none; b=mGWgpAS333HnllfsASAyK9Z7loEc5RY3wK2/3FUBXGaaBF17PAsqWPhJ1Jnqy31pcDsiPS7jBA+kRIoCmCGYT4GrOwbnKoQPQhDvZ9A7HvI9VRZNLVaVD4cXRiOWtS9ctvoMAlnW3Z4o86ptsRcb3SAoEkAI237e3e01maeCT3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706095018; c=relaxed/simple; bh=ynbxT7KzpJ2BKHXeKOVeT8neLB9IPVp7YQoLH0Mmvoo=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=JO0sS1KqSyM4NO2hVIvNHT9/7U+InSztpyohngPrPRBKqbA9C1ntsmgzjkkzZOSRJnCxHgEblgsarEI651h2pky3phzh/6PYt/ODH3ni+D2dBDxb1nTusqu7RUG/CE9FYUCy9vD7iaRE0AQBnVDVAKvJjFCcGKBoO1Fp0BCTxvQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-55ad2a47b7aso4613026a12.3 for ; Wed, 24 Jan 2024 03:16:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1706095013; x=1706699813; darn=gcc.gnu.org; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=DNFikUdvIiT4OlEcBiD/GAaejslLi1534Xv34WHtX2Q=; b=cisrlVv3hE2zhf7nB6WDI5HBLY0rvhy1+fG+XUlVS6jAfOjG6OpZToVINpEK7dDnZz o2R3b4qvw6DWIpLFfyyjsWnBGETor/dDtz8WbPmSZzOiJRbGjjKL5P01tBwERpgcruHx q870Xzxu3DzOufpTcltKhwxdjthntJvvWOpJQkSkzVuIluAd3npEBZzSdZR12Haf0Yn1 LDysiys7T+MdZW3diY3FsvSGehurJJ3enp1uPQBiSZdEpfKHzRGeT5zmjTu+q3gekBta dSIPXUgNNGuIzEoWBP0UjbN+C08w4lLt+HMsCxET5b4L9cOts0Rwq58sKVFxN4LKxAVc klxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706095013; x=1706699813; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=DNFikUdvIiT4OlEcBiD/GAaejslLi1534Xv34WHtX2Q=; b=q7YZyrZXEJjvkmdzmKRuctvFwOu0d42rmDLMEKVop8ifQQCQAFSg7H0Uv8jXHPh4/T g+4hV1u/s14nn46i7Jrw1TSwqpekJ0PMVgMCohy5N17mVcgv6RYpHYtPXH6Zq5CMizET DvvlcovLLhfRSfBu4UBRliQt30NmSzz4+/sJS8R6KHY7KETkWSCNwaMxPwvXzPBTKPyz wkCTxuLfWGc1b9eM+pjkm2evqtfCZhSlQRd4GMmtaGIk+J7XM7qykVyeFhB+oXJuEotD E/Tl70qNIPVC/nWsIgqUU0u8DnTOWFkoBsBzZvoVWfFL3L0M8JTN+rCNCUrmos4DroRK QOzg== X-Gm-Message-State: AOJu0Yx5a/DirsIzfdizETnLlrBUOBgM1TVXkKO4iu8+M/KKGjEE/Jj/ FuN5q0RmmfWEhyi9VhSGFeYLNrGLQsU9oYAsnoRmvaJ11CJisLP6rqI8wpAMJDF7Tw+wi+NaTv+ I X-Google-Smtp-Source: AGHT+IGxnUiq12PY3NDLgtnFPD4C8MdstCFsoMvEE99yN96EOnyWxdpRyJigLj/oA+WSkq2b53KY1g== X-Received: by 2002:a17:907:a805:b0:a31:4083:4d06 with SMTP id vo5-20020a170907a80500b00a3140834d06mr84939ejc.85.1706095013147; Wed, 24 Jan 2024 03:16:53 -0800 (PST) Received: from annie.orcam.me.uk (annie.orcam.me.uk. [78.133.224.48]) by smtp.gmail.com with ESMTPSA id st8-20020a170907c08800b00a2ff7a6b47esm4057378ejc.46.2024.01.24.03.16.52 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Jan 2024 03:16:52 -0800 (PST) Date: Wed, 24 Jan 2024 11:16:51 +0000 (GMT) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org cc: Andrew Waterman , Jim Wilson , Kito Cheng , Palmer Dabbelt Subject: [PATCH 2/2] RISC-V/testsuite: Add RTL cset-sext.c testcase variants In-Reply-To: Message-ID: References: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-0.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_ASCII_DIVIDERS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Add RTL tests, for RV64 and RV32 where appropriate, corresponding to the existing cset-sext.c tests. They have been produced from RTL code as at the entry of the "ce1" pass for the respective cset-sext.c tests built at -O3. gcc/testsuite/ * gcc.target/riscv/cset-sext-rtl.c: New file. * gcc.target/riscv/cset-sext-rtl32.c: New file. * gcc.target/riscv/cset-sext-sfb-rtl.c: New file. * gcc.target/riscv/cset-sext-sfb-rtl32.c: New file. * gcc.target/riscv/cset-sext-thead-rtl.c: New file. * gcc.target/riscv/cset-sext-ventana-rtl.c: New file. * gcc.target/riscv/cset-sext-zicond-rtl.c: New file. * gcc.target/riscv/cset-sext-zicond-rtl32.c: New file. --- gcc/testsuite/gcc.target/riscv/cset-sext-rtl.c | 87 +++++++++++++++ gcc/testsuite/gcc.target/riscv/cset-sext-rtl32.c | 84 +++++++++++++++ gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl.c | 88 ++++++++++++++++ gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl32.c | 85 +++++++++++++++ gcc/testsuite/gcc.target/riscv/cset-sext-thead-rtl.c | 86 +++++++++++++++ gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c | 86 +++++++++++++++ gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl.c | 86 +++++++++++++++ gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl32.c | 83 +++++++++++++++ 8 files changed, 685 insertions(+) gcc-test-riscv-cset-sext-rtl.diff Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-rtl.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-rtl.c @@ -0,0 +1,87 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +int __RTL (startwith ("ce1")) +foo (long a, long b) +{ +(function "foo" + (param "a" + (DECL_RTL (reg/v:DI <2> [ a ])) + (DECL_RTL_INCOMING (reg:DI a0 [ a ]))) + (param "b" + (DECL_RTL (reg/v:DI <3> [ b ])) + (DECL_RTL_INCOMING (reg:DI a1 [ b ]))) + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg/v:DI <2> [ a ]) + (reg:DI a0 [ a ])) "cset-sext.c":8:1 + (expr_list:REG_DEAD (reg:DI a0 [ a ]))) + (cinsn 3 (set (reg/v:DI <3> [ b ]) + (reg:DI a1 [ b ])) "cset-sext.c":8:1 + (expr_list:REG_DEAD (reg:DI a1 [ b ]))) + (cnote 4 NOTE_INSN_FUNCTION_BEG) + (cjump_insn 8 (set (pc) + (if_then_else (eq (reg/v:DI <3> [ b ]) + (const_int 0)) + (label_ref:DI 24) + (pc))) "cset-sext.c":9:6 + (expr_list:REG_DEAD (reg/v:DI <3> [ b ]) + (int_list:REG_BR_PROB 365072228))) + (edge-to 4) + (edge-to 3 (flags "FALLTHRU")) + ) ;; block 2 + (block 3 + (edge-from 2 (flags "FALLTHRU")) + (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) + (cinsn 10 (set (reg:SI <5>) + (ne:SI (reg/v:DI <2> [ a ]) + (const_int 0))) "cset-sext.c":11:11 + (expr_list:REG_DEAD (reg/v:DI <2> [ a ]))) + (cinsn 11 (set (reg:DI <1> [ ]) + (sign_extend:DI (reg:SI <5>))) "cset-sext.c":11:11 + (expr_list:REG_DEAD (reg:SI <5>))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 3 + (block 4 + (edge-from 2) + (clabel 24 3) + (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK) + (cinsn 5 (set (reg:DI <1> [ ]) + (const_int 0)) "cset-sext.c":10:12) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 4 + (block 5 + (edge-from 4 (flags "FALLTHRU")) + (edge-from 3 (flags "FALLTHRU")) + (clabel 12 2) + (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK) + (cinsn 18 (set (reg/i:DI a0) + (reg:DI <1> [ ])) "cset-sext.c":15:1 + (expr_list:REG_DEAD (reg:DI <1> [ ]))) + (cinsn 19 (use (reg/i:DI a0)) "cset-sext.c":15:1) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 5 + ) ;; insn-chain + (crtl + (return_rtx + (reg/i:DI a0) + ) ;; return_rtx + ) ;; crtl +) ;; function "foo" +} + +/* Expect branchless assembly like: + + snez a1,a1 + neg a1,a1 + snez a0,a0 + and a0,a1,a0 + */ + +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssnez\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-rtl32.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-rtl32.c @@ -0,0 +1,84 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv32 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */ + +int __RTL (startwith ("ce1")) +foo (long a, long b) +{ +(function "foo" + (param "a" + (DECL_RTL (reg/v:SI <2> [ a ])) + (DECL_RTL_INCOMING (reg:SI a0 [ a ]))) + (param "b" + (DECL_RTL (reg/v:SI <3> [ b ])) + (DECL_RTL_INCOMING (reg:SI a1 [ b ]))) + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg/v:SI <2> [ a ]) + (reg:SI a0 [ a ])) "cset-sext.c":8:1 + (expr_list:REG_DEAD (reg:SI a0 [ a ]))) + (cinsn 3 (set (reg/v:SI <3> [ b ]) + (reg:SI a1 [ b ])) "cset-sext.c":8:1 + (expr_list:REG_DEAD (reg:SI a1 [ b ]))) + (cnote 4 NOTE_INSN_FUNCTION_BEG) + (cjump_insn 8 (set (pc) + (if_then_else (eq (reg/v:SI <3> [ b ]) + (const_int 0)) + (label_ref:SI 23) + (pc))) "cset-sext.c":9:6 + (int_list:REG_BR_PROB 365072228)) + (edge-to 4) + (edge-to 3 (flags "FALLTHRU")) + ) ;; block 2 + (block 3 + (edge-from 2 (flags "FALLTHRU")) + (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) + (cinsn 10 (set (reg:SI <1> [ ]) + (ne:SI (reg/v:SI <2> [ a ]) + (const_int 0))) "cset-sext.c":11:11 + (expr_list:REG_DEAD (reg/v:SI <2> [ a ]))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 3 + (block 4 + (edge-from 2) + (clabel 23 3) + (cnote 22 [bb 4] NOTE_INSN_BASIC_BLOCK) + (cinsn 5 (set (reg:SI <1> [ ]) + (const_int 0)) "cset-sext.c":10:12 + (expr_list:REG_DEAD (reg/v:SI <3> [ b ]))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 4 + (block 5 + (edge-from 4 (flags "FALLTHRU")) + (edge-from 3 (flags "FALLTHRU")) + (clabel 16 1) + (cnote 19 [bb 5] NOTE_INSN_BASIC_BLOCK) + (cinsn 17 (set (reg/i:SI a0) + (reg:SI <1> [ ])) "cset-sext.c":15:1 + (expr_list:REG_DEAD (reg:SI <1> [ ]))) + (cinsn 18 (use (reg/i:SI a0)) "cset-sext.c":15:1) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 5 + ) ;; insn-chain + (crtl + (return_rtx + (reg/i:SI a0) + ) ;; return_rtx + ) ;; crtl +) ;; function "foo" +} + +/* Expect branchless assembly like: + + snez a1,a1 + neg a1,a1 + snez a0,a0 + and a0,a1,a0 + */ + +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssnez\\s" 2 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */ + +int __RTL (startwith ("ce1")) +foo (long a, long b) +{ +(function "foo" + (param "a" + (DECL_RTL (reg/v:DI <2> [ a ])) + (DECL_RTL_INCOMING (reg:DI a0 [ a ]))) + (param "b" + (DECL_RTL (reg/v:DI <3> [ b ])) + (DECL_RTL_INCOMING (reg:DI a1 [ b ]))) + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg/v:DI <2> [ a ]) + (reg:DI a0 [ a ])) "cset-sext-sfb.c":8:1 + (expr_list:REG_DEAD (reg:DI a0 [ a ]))) + (cinsn 3 (set (reg/v:DI <3> [ b ]) + (reg:DI a1 [ b ])) "cset-sext-sfb.c":8:1 + (expr_list:REG_DEAD (reg:DI a1 [ b ]))) + (cnote 4 NOTE_INSN_FUNCTION_BEG) + (cjump_insn 8 (set (pc) + (if_then_else (eq (reg/v:DI <3> [ b ]) + (const_int 0)) + (label_ref:DI 24) + (pc))) "cset-sext-sfb.c":9:6 + (expr_list:REG_DEAD (reg/v:DI <3> [ b ]) + (int_list:REG_BR_PROB 365072228))) + (edge-to 4) + (edge-to 3 (flags "FALLTHRU")) + ) ;; block 2 + (block 3 + (edge-from 2 (flags "FALLTHRU")) + (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) + (cinsn 10 (set (reg:SI <5>) + (ne:SI (reg/v:DI <2> [ a ]) + (const_int 0))) "cset-sext-sfb.c":11:11 + (expr_list:REG_DEAD (reg/v:DI <2> [ a ]))) + (cinsn 11 (set (reg:DI <1> [ ]) + (sign_extend:DI (reg:SI <5>))) "cset-sext-sfb.c":11:11 + (expr_list:REG_DEAD (reg:SI <5>))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 3 + (block 4 + (edge-from 2) + (clabel 24 3) + (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK) + (cinsn 5 (set (reg:DI <1> [ ]) + (const_int 0)) "cset-sext-sfb.c":10:12) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 4 + (block 5 + (edge-from 4 (flags "FALLTHRU")) + (edge-from 3 (flags "FALLTHRU")) + (clabel 12 2) + (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK) + (cinsn 18 (set (reg/i:DI a0) + (reg:DI <1> [ ])) "cset-sext-sfb.c":15:1 + (expr_list:REG_DEAD (reg:DI <1> [ ]))) + (cinsn 19 (use (reg/i:DI a0)) "cset-sext-sfb.c":15:1) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 5 + ) ;; insn-chain + (crtl + (return_rtx + (reg/i:DI a0) + ) ;; return_rtx + ) ;; crtl +) ;; function "foo" +} + +/* Expect short forward branch assembly like: + + snez a0,a0 + bne a1,zero,1f # movcc + mv a0,zero +1: + */ + +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbne\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbeq\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl32.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl32.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv32 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */ + +int __RTL (startwith ("ce1")) +foo (long a, long b) +{ +(function "foo" + (param "a" + (DECL_RTL (reg/v:SI <2> [ a ])) + (DECL_RTL_INCOMING (reg:SI a0 [ a ]))) + (param "b" + (DECL_RTL (reg/v:SI <3> [ b ])) + (DECL_RTL_INCOMING (reg:SI a1 [ b ]))) + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg/v:SI <2> [ a ]) + (reg:SI a0 [ a ])) "cset-sext-sfb.c":8:1 + (expr_list:REG_DEAD (reg:SI a0 [ a ]))) + (cinsn 3 (set (reg/v:SI <3> [ b ]) + (reg:SI a1 [ b ])) "cset-sext-sfb.c":8:1 + (expr_list:REG_DEAD (reg:SI a1 [ b ]))) + (cnote 4 NOTE_INSN_FUNCTION_BEG) + (cjump_insn 8 (set (pc) + (if_then_else (eq (reg/v:SI <3> [ b ]) + (const_int 0)) + (label_ref:SI 23) + (pc))) "cset-sext-sfb.c":9:6 + (int_list:REG_BR_PROB 365072228)) + (edge-to 4) + (edge-to 3 (flags "FALLTHRU")) + ) ;; block 2 + (block 3 + (edge-from 2 (flags "FALLTHRU")) + (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) + (cinsn 10 (set (reg:SI <1> [ ]) + (ne:SI (reg/v:SI <2> [ a ]) + (const_int 0))) "cset-sext-sfb.c":11:11 + (expr_list:REG_DEAD (reg/v:SI <2> [ a ]))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 3 + (block 4 + (edge-from 2) + (clabel 23 3) + (cnote 22 [bb 4] NOTE_INSN_BASIC_BLOCK) + (cinsn 5 (set (reg:SI <1> [ ]) + (const_int 0)) "cset-sext-sfb.c":10:12 + (expr_list:REG_DEAD (reg/v:SI <3> [ b ]))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 4 + (block 5 + (edge-from 4 (flags "FALLTHRU")) + (edge-from 3 (flags "FALLTHRU")) + (clabel 16 1) + (cnote 19 [bb 5] NOTE_INSN_BASIC_BLOCK) + (cinsn 17 (set (reg/i:SI a0) + (reg:SI <1> [ ])) "cset-sext-sfb.c":15:1 + (expr_list:REG_DEAD (reg:SI <1> [ ]))) + (cinsn 18 (use (reg/i:SI a0)) "cset-sext-sfb.c":15:1) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 5 + ) ;; insn-chain + (crtl + (return_rtx + (reg/i:SI a0) + ) ;; return_rtx + ) ;; crtl +) ;; function "foo" +} + +/* Expect short forward branch assembly like: + + snez a0,a0 + bne a1,zero,1f # movcc + mv a0,zero +1: + */ + +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sbne\\s\[^\\s\]+\\s# movcc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\sbeq\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-thead-rtl.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-thead-rtl.c @@ -0,0 +1,86 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */ + +int __RTL (startwith ("ce1")) +foo (long a, long b) +{ +(function "foo" + (param "a" + (DECL_RTL (reg/v:DI <2> [ a ])) + (DECL_RTL_INCOMING (reg:DI a0 [ a ]))) + (param "b" + (DECL_RTL (reg/v:DI <3> [ b ])) + (DECL_RTL_INCOMING (reg:DI a1 [ b ]))) + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg/v:DI <2> [ a ]) + (reg:DI a0 [ a ])) "cset-sext-thead.c":8:1 + (expr_list:REG_DEAD (reg:DI a0 [ a ]))) + (cinsn 3 (set (reg/v:DI <3> [ b ]) + (reg:DI a1 [ b ])) "cset-sext-thead.c":8:1 + (expr_list:REG_DEAD (reg:DI a1 [ b ]))) + (cnote 4 NOTE_INSN_FUNCTION_BEG) + (cjump_insn 8 (set (pc) + (if_then_else (eq (reg/v:DI <3> [ b ]) + (const_int 0)) + (label_ref:DI 24) + (pc))) "cset-sext-thead.c":9:6 + (expr_list:REG_DEAD (reg/v:DI <3> [ b ]) + (int_list:REG_BR_PROB 365072228))) + (edge-to 4) + (edge-to 3 (flags "FALLTHRU")) + ) ;; block 2 + (block 3 + (edge-from 2 (flags "FALLTHRU")) + (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) + (cinsn 10 (set (reg:SI <5>) + (ne:SI (reg/v:DI <2> [ a ]) + (const_int 0))) "cset-sext-thead.c":11:11 + (expr_list:REG_DEAD (reg/v:DI <2> [ a ]))) + (cinsn 11 (set (reg:DI <1> [ ]) + (sign_extend:DI (reg:SI <5>))) "cset-sext-thead.c":11:11 + (expr_list:REG_DEAD (reg:SI <5>))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 3 + (block 4 + (edge-from 2) + (clabel 24 3) + (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK) + (cinsn 5 (set (reg:DI <1> [ ]) + (const_int 0)) "cset-sext-thead.c":10:12) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 4 + (block 5 + (edge-from 4 (flags "FALLTHRU")) + (edge-from 3 (flags "FALLTHRU")) + (clabel 12 2) + (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK) + (cinsn 18 (set (reg/i:DI a0) + (reg:DI <1> [ ])) "cset-sext-thead.c":15:1 + (expr_list:REG_DEAD (reg:DI <1> [ ]))) + (cinsn 19 (use (reg/i:DI a0)) "cset-sext-thead.c":15:1) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 5 + ) ;; insn-chain + (crtl + (return_rtx + (reg/i:DI a0) + ) ;; return_rtx + ) ;; crtl +) ;; function "foo" +} + +/* Expect branchless assembly like: + + snez a0,a0 + th.mveqz a0,zero,a1 + */ + +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c @@ -0,0 +1,86 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +int __RTL (startwith ("ce1")) +foo (long a, long b) +{ +(function "foo" + (param "a" + (DECL_RTL (reg/v:DI <2> [ a ])) + (DECL_RTL_INCOMING (reg:DI a0 [ a ]))) + (param "b" + (DECL_RTL (reg/v:DI <3> [ b ])) + (DECL_RTL_INCOMING (reg:DI a1 [ b ]))) + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg/v:DI <2> [ a ]) + (reg:DI a0 [ a ])) "cset-sext-ventana.c":8:1 + (expr_list:REG_DEAD (reg:DI a0 [ a ]))) + (cinsn 3 (set (reg/v:DI <3> [ b ]) + (reg:DI a1 [ b ])) "cset-sext-ventana.c":8:1 + (expr_list:REG_DEAD (reg:DI a1 [ b ]))) + (cnote 4 NOTE_INSN_FUNCTION_BEG) + (cjump_insn 8 (set (pc) + (if_then_else (eq (reg/v:DI <3> [ b ]) + (const_int 0)) + (label_ref:DI 24) + (pc))) "cset-sext-ventana.c":9:6 + (expr_list:REG_DEAD (reg/v:DI <3> [ b ]) + (int_list:REG_BR_PROB 365072228))) + (edge-to 4) + (edge-to 3 (flags "FALLTHRU")) + ) ;; block 2 + (block 3 + (edge-from 2 (flags "FALLTHRU")) + (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) + (cinsn 10 (set (reg:SI <5>) + (ne:SI (reg/v:DI <2> [ a ]) + (const_int 0))) "cset-sext-ventana.c":11:11 + (expr_list:REG_DEAD (reg/v:DI <2> [ a ]))) + (cinsn 11 (set (reg:DI <1> [ ]) + (sign_extend:DI (reg:SI <5>))) "cset-sext-ventana.c":11:11 + (expr_list:REG_DEAD (reg:SI <5>))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 3 + (block 4 + (edge-from 2) + (clabel 24 3) + (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK) + (cinsn 5 (set (reg:DI <1> [ ]) + (const_int 0)) "cset-sext-ventana.c":10:12) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 4 + (block 5 + (edge-from 4 (flags "FALLTHRU")) + (edge-from 3 (flags "FALLTHRU")) + (clabel 12 2) + (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK) + (cinsn 18 (set (reg/i:DI a0) + (reg:DI <1> [ ])) "cset-sext-ventana.c":15:1 + (expr_list:REG_DEAD (reg:DI <1> [ ]))) + (cinsn 19 (use (reg/i:DI a0)) "cset-sext-ventana.c":15:1) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 5 + ) ;; insn-chain + (crtl + (return_rtx + (reg/i:DI a0) + ) ;; return_rtx + ) ;; crtl +) ;; function "foo" +} + +/* Expect branchless assembly like: + + snez a0,a0 + vt.maskc a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl.c @@ -0,0 +1,86 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +int __RTL (startwith ("ce1")) +foo (long a, long b) +{ +(function "foo" + (param "a" + (DECL_RTL (reg/v:DI <2> [ a ])) + (DECL_RTL_INCOMING (reg:DI a0 [ a ]))) + (param "b" + (DECL_RTL (reg/v:DI <3> [ b ])) + (DECL_RTL_INCOMING (reg:DI a1 [ b ]))) + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg/v:DI <2> [ a ]) + (reg:DI a0 [ a ])) "cset-sext-zicond.c":8:1 + (expr_list:REG_DEAD (reg:DI a0 [ a ]))) + (cinsn 3 (set (reg/v:DI <3> [ b ]) + (reg:DI a1 [ b ])) "cset-sext-zicond.c":8:1 + (expr_list:REG_DEAD (reg:DI a1 [ b ]))) + (cnote 4 NOTE_INSN_FUNCTION_BEG) + (cjump_insn 8 (set (pc) + (if_then_else (eq (reg/v:DI <3> [ b ]) + (const_int 0)) + (label_ref:DI 24) + (pc))) "cset-sext-zicond.c":9:6 + (expr_list:REG_DEAD (reg/v:DI <3> [ b ]) + (int_list:REG_BR_PROB 365072228))) + (edge-to 4) + (edge-to 3 (flags "FALLTHRU")) + ) ;; block 2 + (block 3 + (edge-from 2 (flags "FALLTHRU")) + (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) + (cinsn 10 (set (reg:SI <5>) + (ne:SI (reg/v:DI <2> [ a ]) + (const_int 0))) "cset-sext-zicond.c":11:11 + (expr_list:REG_DEAD (reg/v:DI <2> [ a ]))) + (cinsn 11 (set (reg:DI <1> [ ]) + (sign_extend:DI (reg:SI <5>))) "cset-sext-zicond.c":11:11 + (expr_list:REG_DEAD (reg:SI <5>))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 3 + (block 4 + (edge-from 2) + (clabel 24 3) + (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK) + (cinsn 5 (set (reg:DI <1> [ ]) + (const_int 0)) "cset-sext-zicond.c":10:12) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 4 + (block 5 + (edge-from 4 (flags "FALLTHRU")) + (edge-from 3 (flags "FALLTHRU")) + (clabel 12 2) + (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK) + (cinsn 18 (set (reg/i:DI a0) + (reg:DI <1> [ ])) "cset-sext-zicond.c":15:1 + (expr_list:REG_DEAD (reg:DI <1> [ ]))) + (cinsn 19 (use (reg/i:DI a0)) "cset-sext-zicond.c":15:1) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 5 + ) ;; insn-chain + (crtl + (return_rtx + (reg/i:DI a0) + ) ;; return_rtx + ) ;; crtl +) ;; function "foo" +} + +/* Expect branchless assembly like: + + snez a0,a0 + czero.eqz a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl32.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl32.c @@ -0,0 +1,83 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv32 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +int __RTL (startwith ("ce1")) +foo (long a, long b) +{ +(function "foo" + (param "a" + (DECL_RTL (reg/v:SI <2> [ a ])) + (DECL_RTL_INCOMING (reg:SI a0 [ a ]))) + (param "b" + (DECL_RTL (reg/v:SI <3> [ b ])) + (DECL_RTL_INCOMING (reg:SI a1 [ b ]))) + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg/v:SI <2> [ a ]) + (reg:SI a0 [ a ])) "cset-sext-zicond.c":8:1 + (expr_list:REG_DEAD (reg:SI a0 [ a ]))) + (cinsn 3 (set (reg/v:SI <3> [ b ]) + (reg:SI a1 [ b ])) "cset-sext-zicond.c":8:1 + (expr_list:REG_DEAD (reg:SI a1 [ b ]))) + (cnote 4 NOTE_INSN_FUNCTION_BEG) + (cjump_insn 8 (set (pc) + (if_then_else (eq (reg/v:SI <3> [ b ]) + (const_int 0)) + (label_ref:SI 23) + (pc))) "cset-sext-zicond.c":9:6 + (int_list:REG_BR_PROB 365072228)) + (edge-to 4) + (edge-to 3 (flags "FALLTHRU")) + ) ;; block 2 + (block 3 + (edge-from 2 (flags "FALLTHRU")) + (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK) + (cinsn 10 (set (reg:SI <1> [ ]) + (ne:SI (reg/v:SI <2> [ a ]) + (const_int 0))) "cset-sext-zicond.c":11:11 + (expr_list:REG_DEAD (reg/v:SI <2> [ a ]))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 3 + (block 4 + (edge-from 2) + (clabel 23 3) + (cnote 22 [bb 4] NOTE_INSN_BASIC_BLOCK) + (cinsn 5 (set (reg:SI <1> [ ]) + (const_int 0)) "cset-sext-zicond.c":10:12 + (expr_list:REG_DEAD (reg/v:SI <3> [ b ]))) + (edge-to 5 (flags "FALLTHRU")) + ) ;; block 4 + (block 5 + (edge-from 4 (flags "FALLTHRU")) + (edge-from 3 (flags "FALLTHRU")) + (clabel 16 1) + (cnote 19 [bb 5] NOTE_INSN_BASIC_BLOCK) + (cinsn 17 (set (reg/i:SI a0) + (reg:SI <1> [ ])) "cset-sext-zicond.c":15:1 + (expr_list:REG_DEAD (reg:SI <1> [ ]))) + (cinsn 18 (use (reg/i:SI a0)) "cset-sext-zicond.c":15:1) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 5 + ) ;; insn-chain + (crtl + (return_rtx + (reg/i:SI a0) + ) ;; return_rtx + ) ;; crtl +) ;; function "foo" +} + +/* Expect branchless assembly like: + + snez a0,a0 + czero.eqz a0,a0,a1 + */ + +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */