From patchwork Mon Jun 3 16:26:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 248338 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 6C8BA2C009A for ; Tue, 4 Jun 2013 02:29:19 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=gOvPdodXnLAhILItjwR UGxy0C15dfG+EELS1uaLt9EsuljsDVwHTfRIVZlL4kSD6K2f80qUkhtGXF5+NBmm tace+av0ow4dQ0OGjQLP5cLt+/beXW8dRPasaXA7I8f5F+915qmWe3C/yGi9QYRx /Im2lH/5IxE1ERah6pvQJKik= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=TAYho4ZTKidC1SgeEzPyRZk90 8A=; b=aaHqNU40oJwVQLHuizZ2xwyITGtVwUMQBkCn46HHmFYuPMU5egzpQUAbb Y9kM6iB8Cknrxt7w4UJk6aRuXyq6fpOFG099VlyC72mBjfwJ0IRGrKDRsXzHSPfC WzqnzYftaEANTP1G9oTaJYMJi3eYnc4lwNE0q+zuuHHIAH5gws= Received: (qmail 9313 invoked by alias); 3 Jun 2013 16:27:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9288 invoked by uid 89); 3 Jun 2013 16:27:46 -0000 X-Spam-SWARE-Status: No, score=-3.1 required=5.0 tests=AWL, BAYES_00, KHOP_THREADED, RP_MATCHES_RCVD autolearn=ham version=3.3.1 Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Mon, 03 Jun 2013 16:27:45 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id r53GRWfa005185; Mon, 3 Jun 2013 09:27:32 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id r53GRWmg005184; Mon, 3 Jun 2013 09:27:32 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH v2 6/6] rs6000: dot for ashiftrt Date: Mon, 3 Jun 2013 09:26:56 -0700 Message-Id: In-Reply-To: References: In-Reply-To: References: Last for now: move ashiftrt to integer.mdm. 2013-06-03 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (ashrsi3, ashrdi3_no_power, ashrdisi3_noppc64be, ashrdi3, ashrdi3_internal1, ashrdi3_internal2, ashrdi3_internal3): Delete. (ashr3, ashr3_imm): New. * config/rs6000/integer.md: Regenerate. --- gcc/config/rs6000/integer.md | 156 ++++++++++++++++++++++++++++++++ gcc/config/rs6000/integer.mdm | 18 ++++ gcc/config/rs6000/rs6000.md | 201 ------------------------------------------ 3 files changed, 174 insertions(+), 201 deletions(-) diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md index b075166..90c6632 100644 --- a/gcc/config/rs6000/integer.md +++ b/gcc/config/rs6000/integer.md @@ -348,6 +348,162 @@ (define_split (const_int 0)))] "") +(define_insn "ashr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "sra %0,%1,%2" + [(set_attr "type" "var_shift_rotate")]) + +(define_insn "*ashr3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "(mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode" + "@ + sra. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*ashr3_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (ashiftrt:GPR (match_dup 1) + (match_dup 2)))] + "(mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode" + "@ + sra. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (ashiftrt:GPR (match_dup 1) + (match_dup 2)))] + "((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*ashr3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + "srai %0,%1,%2" + [(set_attr "type" "shift")]) + +(define_insn "*ashr3_imm_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && ((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode)" + "@ + srai. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "shift")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && ((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode)) + && (reload_completed)" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*ashr3_imm_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (ashiftrt:GPR (match_dup 1) + (match_dup 2)))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && ((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode)" + "@ + srai. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "shift")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (ashiftrt:GPR (match_dup 1) + (match_dup 2)))] + "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && ((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode)) + && (reload_completed)" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + ; -- Logical instructions: ; andi., andis., ori, oris, xori, xoris diff --git a/gcc/config/rs6000/integer.mdm b/gcc/config/rs6000/integer.mdm index 3147478..fe83f7d 100644 --- a/gcc/config/rs6000/integer.mdm +++ b/gcc/config/rs6000/integer.mdm @@ -65,6 +65,24 @@ "sri %0,%1,%2" [(set_attr "type" "shift")]) +(define_dot_insn "ashr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "(mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode" + "sra %0,%1,%2" + [(set_attr "type" "var_shift_rotate")]) + +(define_dot_insn "*ashr3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + "(mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode" + "srai %0,%1,%2" + [(set_attr "type" "shift")]) + ; -- Logical instructions: ; andi., andis., ori, oris, xori, xoris diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8765340..fb074a7 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4620,16 +4620,6 @@ (define_split (const_int 0)))] "") -(define_insn "ashrsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "" - "@ - sraw %0,%1,%2 - srawi %0,%1,%h2" - [(set_attr "type" "var_shift_rotate,shift")]) - (define_insn "*ashrsi3_64" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (sign_extend:DI @@ -4640,51 +4630,6 @@ (define_insn "*ashrsi3_64" sraw %0,%1,%2 srawi %0,%1,%h2" [(set_attr "type" "var_shift_rotate,shift")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "" - "@ - sraw. %3,%1,%2 - srawi. %3,%1,%h2 - # - #" - [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (ashiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "" - "@ - sraw. %0,%1,%2 - srawi. %0,%1,%h2 - # - #" - [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") - (set_attr "length" "4,4,8,8")]) ;; Builtins to replace a division to generate FRE reciprocal estimate ;; instructions and the necessary fixup instructions @@ -4725,21 +4670,6 @@ (define_expand "rsqrt2" DONE; }) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ashiftrt:SI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (ashiftrt:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - ;; Floating-point insns, excluding normal data motion. ;; ;; PowerPC has a full set of single-precision floating point instructions. @@ -6490,49 +6420,6 @@ (define_insn "umulsi3_highpart" "" "mulhwu %0,%1,%2" [(set_attr "type" "imul")]) - -;; Shift by a variable amount is too complex to be worth open-coding. We -;; just handle shifts by constants. -(define_insn "ashrdi3_no_power" - [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") - (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "M,i")))] - "!TARGET_POWERPC64" - "* -{ - switch (which_alternative) - { - default: - gcc_unreachable (); - case 0: - if (WORDS_BIG_ENDIAN) - return \"srawi %0,%1,31\;srawi %L0,%1,%h2\"; - else - return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\"; - case 1: - if (WORDS_BIG_ENDIAN) - return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\"; - else - return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\"; - } -}" - [(set_attr "type" "two,three") - (set_attr "length" "8,12")]) - -(define_insn "*ashrdisi3_noppc64be" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (const_int 32)) 4))] - "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN" - "* -{ - if (REGNO (operands[0]) == REGNO (operands[1])) - return \"\"; - else - return \"mr %0,%1\"; -}" - [(set_attr "length" "4")]) - ;; PowerPC64 DImode operations. @@ -7454,94 +7341,6 @@ (define_split (const_int 0)))] "") -(define_expand "ashrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")))] - "" - " -{ - if (TARGET_POWERPC64) - ; - else if (GET_CODE (operands[2]) == CONST_INT) - { - emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); - DONE; - } - else - FAIL; -}") - -(define_insn "*ashrdi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" - "@ - srad %0,%1,%2 - sradi %0,%1,%H2" - [(set_attr "type" "var_shift_rotate,shift")]) - -(define_insn "*ashrdi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT" - "@ - srad. %3,%1,%2 - sradi. %3,%1,%H2 - # - #" - [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ashiftrt:DI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*ashrdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - srad. %0,%1,%2 - sradi. %0,%1,%H2 - # - #" - [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ashiftrt:DI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_expand "anddi3" [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")