diff mbox series

[5/11] Change TARGET_FPRND to TARGET_POWER5X

Message ID Zxv1f1LTEd82BsSy@cowardly-lion.the-meissners.org
State New
Headers show
Series Separate PowerPC architecture bits from ISA flags that use command line options | expand

Commit Message

Michael Meissner Oct. 25, 2024, 7:46 p.m. UTC 
As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER5X.  The FPRND instruction was added in power5+.

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define (like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
this test for all supported combinations of -mcpu, big/little endian, and 32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-10-25  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.cc (report_architecture_mismatch): Use
	TARGET_POWER5X instead of TARGET_FPRND.
	* config/rs6000/rs6000.md (fmod<mode>3): Use TARGET_POWER5X instead of
	TARGET_FPRND.
	(remainder<mode>3): Likewise.
	(fctiwuz_<mode>): Likewise.
	(btrunc<mode>2): Likewise.
	(ceil<mode>2): Likewise.
	(floor<mode>2): Likewise.
	(round<mode>): Likewise.
---
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/config/rs6000/rs6000.md | 14 +++++++-------
 2 files changed, 8 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a944ffde28a..dd51d75c495 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -25428,7 +25428,7 @@  report_architecture_mismatch (void)
     rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
     rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
     rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POPCNTB)
     rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 10d13bf812d..7f9fe609a03 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@  (define_expand "fmod<mode>3"
 	(use (match_operand:SFDF 1 "gpc_reg_operand"))
 	(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
    && flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (<MODE>mode);
@@ -5189,7 +5189,7 @@  (define_expand "remainder<mode>3"
 	(use (match_operand:SFDF 1 "gpc_reg_operand"))
 	(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
    && flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (<MODE>mode);
@@ -6687,7 +6687,7 @@  (define_insn "fctiwuz_<mode>"
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
    && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
    friz %0,%1
@@ -6815,7 +6815,7 @@  (define_insn "btrunc<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
    friz %0,%1
    xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@  (define_insn "ceil<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
    frip %0,%1
    xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@  (define_insn "floor<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
    frim %0,%1
    xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@  (define_insn "round<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
 	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
 		     UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_attr "type" "fp")])