| Message ID | Yjj0riWl1Cj0WeUL@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] x86: Disable SSE in ISA2 for -mgeneral-regs-only | expand |
On Mon, Mar 21, 2022 at 10:57 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Mon, Mar 21, 2022 at 10:50:11PM +0100, Uros Bizjak wrote: > > On Mon, Mar 21, 2022 at 10:47 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > > > On Mon, Mar 21, 2022 at 10:23:59PM +0100, Uros Bizjak wrote: > > > > On Mon, Mar 21, 2022 at 10:10 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > > > > > > > SSE and AVX ISAs in ISA2 should be disabled for -mgeneral-regs-only. > > > > > > > > > > gcc/ > > > > > > > > > > PR target/105000 > > > > > * common/config/i386/i386-common.cc > > > > > (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Also disable SSE > > > > > and AVX. > > > > > > > > > > gcc/testsuite/ > > > > > > > > > > PR target/105000 > > > > > * gcc.target/i386/pr105000-1.c: New test. > > > > > * gcc.target/i386/pr105000-2.c: Likewise. > > > > > * gcc.target/i386/pr105000-3.c: Likewise. > > > > > --- > > > > > gcc/common/config/i386/i386-common.cc | 4 +++- > > > > > gcc/testsuite/gcc.target/i386/pr105000-1.c | 11 +++++++++++ > > > > > gcc/testsuite/gcc.target/i386/pr105000-2.c | 11 +++++++++++ > > > > > gcc/testsuite/gcc.target/i386/pr105000-3.c | 11 +++++++++++ > > > > > 4 files changed, 36 insertions(+), 1 deletion(-) > > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-1.c > > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-2.c > > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-3.c > > > > > > > > > > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc > > > > > index 449df6351c9..b77d495e9a4 100644 > > > > > --- a/gcc/common/config/i386/i386-common.cc > > > > > +++ b/gcc/common/config/i386/i386-common.cc > > > > > @@ -321,7 +321,9 @@ along with GCC; see the file COPYING3. If not see > > > > > | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ > > > > > | OPTION_MASK_ISA2_AVX512FP16_UNSET) > > > > > #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ > > > > > - (OPTION_MASK_ISA2_AVX512F_UNSET) > > > > > + (OPTION_MASK_ISA2_SSE_UNSET \ > > > > > + | OPTION_MASK_ISA2_AVX_UNSET \ > > > > > + | OPTION_MASK_ISA2_AVX512F_UNSET) > > > > > > > > The above should only need OPTION_MASK_ISA2_SSE_UNSET, other options > > > > follow from #define chain. > > > > > > > > > > Here is the v2 patch to use OPTION_MASK_ISA2_SSE_UNSET. OK for > > > master and GCC 11 branches? > > > > Have you regressiont tested it? > > I tested with the original patch. Since OPTION_MASK_ISA2_SSE_UNSET > is the same as > > (OPTION_MASK_ISA2_SSE_UNSET > | OPTION_MASK_ISA2_AVX_UNSET > | OPTION_MASK_ISA2_AVX512F_UNSET) > > there should be no difference. I hope so. OK. Thanks, Uros. > > > > > > Thanks. > > > > > > > > > H.J. > > > --- > > > Replace OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET > > > in OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET to disable SSE, AVX and > > > AVX512 ISAs. > > > > > > gcc/ > > > > > > PR target/105000 > > > * common/config/i386/i386-common.cc > > > (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace > > > OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET. > > > > > > gcc/testsuite/ > > > > > > PR target/105000 > > > * gcc.target/i386/pr105000-1.c: New test. > > > * gcc.target/i386/pr105000-2.c: Likewise. > > > * gcc.target/i386/pr105000-3.c: Likewise. > > > * gcc.target/i386/pr105000-4.c: Likewise. > > > --- > > > gcc/common/config/i386/i386-common.cc | 2 +- > > > gcc/testsuite/gcc.target/i386/pr105000-1.c | 11 +++++++++++ > > > gcc/testsuite/gcc.target/i386/pr105000-2.c | 11 +++++++++++ > > > gcc/testsuite/gcc.target/i386/pr105000-3.c | 11 +++++++++++ > > > gcc/testsuite/gcc.target/i386/pr105000-4.c | 11 +++++++++++ > > > 5 files changed, 45 insertions(+), 1 deletion(-) > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-1.c > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-2.c > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-3.c > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-4.c > > > > > > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc > > > index 449df6351c9..c64d7b01126 100644 > > > --- a/gcc/common/config/i386/i386-common.cc > > > +++ b/gcc/common/config/i386/i386-common.cc > > > @@ -321,7 +321,7 @@ along with GCC; see the file COPYING3. If not see > > > | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ > > > | OPTION_MASK_ISA2_AVX512FP16_UNSET) > > > #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ > > > - (OPTION_MASK_ISA2_AVX512F_UNSET) > > > + (OPTION_MASK_ISA2_SSE_UNSET) > > > > No need for parenthesis. > > > > Fixed in the v3 patch. > > > H.J. > --- > Replace OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET > in OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET to disable SSE, AVX and > AVX512 ISAs. > > gcc/ > > PR target/105000 > * common/config/i386/i386-common.cc > (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace > OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET. > > gcc/testsuite/ > > PR target/105000 > * gcc.target/i386/pr105000-1.c: New test. > * gcc.target/i386/pr105000-2.c: Likewise. > * gcc.target/i386/pr105000-3.c: Likewise. > * gcc.target/i386/pr105000-4.c: Likewise. > --- > gcc/common/config/i386/i386-common.cc | 2 +- > gcc/testsuite/gcc.target/i386/pr105000-1.c | 11 +++++++++++ > gcc/testsuite/gcc.target/i386/pr105000-2.c | 11 +++++++++++ > gcc/testsuite/gcc.target/i386/pr105000-3.c | 11 +++++++++++ > gcc/testsuite/gcc.target/i386/pr105000-4.c | 11 +++++++++++ > 5 files changed, 45 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-2.c > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-3.c > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-4.c > > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc > index 449df6351c9..07fdd045f30 100644 > --- a/gcc/common/config/i386/i386-common.cc > +++ b/gcc/common/config/i386/i386-common.cc > @@ -321,7 +321,7 @@ along with GCC; see the file COPYING3. If not see > | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ > | OPTION_MASK_ISA2_AVX512FP16_UNSET) > #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ > - (OPTION_MASK_ISA2_AVX512F_UNSET) > + OPTION_MASK_ISA2_SSE_UNSET > #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET > #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET > #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET > diff --git a/gcc/testsuite/gcc.target/i386/pr105000-1.c b/gcc/testsuite/gcc.target/i386/pr105000-1.c > new file mode 100644 > index 00000000000..020e2adca83 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr105000-1.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mshstk -mavxvnni" } */ > + > +#include <x86gprintrin.h> > + > +__attribute__((target("no-mmx,no-sse"))) > +int > +foo () > +{ > + return _get_ssp (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/pr105000-2.c b/gcc/testsuite/gcc.target/i386/pr105000-2.c > new file mode 100644 > index 00000000000..a113fd1dfa2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr105000-2.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mshstk -mkl" } */ > + > +#include <x86gprintrin.h> > + > +__attribute__((target("no-mmx,no-sse"))) > +int > +foo () > +{ > + return _get_ssp (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/pr105000-3.c b/gcc/testsuite/gcc.target/i386/pr105000-3.c > new file mode 100644 > index 00000000000..7e82925270c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr105000-3.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mshstk -mwidekl" } */ > + > +#include <x86gprintrin.h> > + > +__attribute__((target("no-mmx,no-sse"))) > +int > +foo () > +{ > + return _get_ssp (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/pr105000-4.c b/gcc/testsuite/gcc.target/i386/pr105000-4.c > new file mode 100644 > index 00000000000..195eabe85a2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr105000-4.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mshstk -mavx512fp16" } */ > + > +#include <x86gprintrin.h> > + > +__attribute__((target("no-mmx,no-sse"))) > +int > +foo () > +{ > + return _get_ssp (); > +} > -- > 2.35.1 >
On Mon, Mar 21, 2022 at 2:59 PM Uros Bizjak <ubizjak@gmail.com> wrote: > > On Mon, Mar 21, 2022 at 10:57 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > On Mon, Mar 21, 2022 at 10:50:11PM +0100, Uros Bizjak wrote: > > > On Mon, Mar 21, 2022 at 10:47 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > > > > > On Mon, Mar 21, 2022 at 10:23:59PM +0100, Uros Bizjak wrote: > > > > > On Mon, Mar 21, 2022 at 10:10 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > > > > > > > > > SSE and AVX ISAs in ISA2 should be disabled for -mgeneral-regs-only. > > > > > > > > > > > > gcc/ > > > > > > > > > > > > PR target/105000 > > > > > > * common/config/i386/i386-common.cc > > > > > > (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Also disable SSE > > > > > > and AVX. > > > > > > > > > > > > gcc/testsuite/ > > > > > > > > > > > > PR target/105000 > > > > > > * gcc.target/i386/pr105000-1.c: New test. > > > > > > * gcc.target/i386/pr105000-2.c: Likewise. > > > > > > * gcc.target/i386/pr105000-3.c: Likewise. > > > > > > --- > > > > > > gcc/common/config/i386/i386-common.cc | 4 +++- > > > > > > gcc/testsuite/gcc.target/i386/pr105000-1.c | 11 +++++++++++ > > > > > > gcc/testsuite/gcc.target/i386/pr105000-2.c | 11 +++++++++++ > > > > > > gcc/testsuite/gcc.target/i386/pr105000-3.c | 11 +++++++++++ > > > > > > 4 files changed, 36 insertions(+), 1 deletion(-) > > > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-1.c > > > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-2.c > > > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-3.c > > > > > > > > > > > > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc > > > > > > index 449df6351c9..b77d495e9a4 100644 > > > > > > --- a/gcc/common/config/i386/i386-common.cc > > > > > > +++ b/gcc/common/config/i386/i386-common.cc > > > > > > @@ -321,7 +321,9 @@ along with GCC; see the file COPYING3. If not see > > > > > > | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ > > > > > > | OPTION_MASK_ISA2_AVX512FP16_UNSET) > > > > > > #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ > > > > > > - (OPTION_MASK_ISA2_AVX512F_UNSET) > > > > > > + (OPTION_MASK_ISA2_SSE_UNSET \ > > > > > > + | OPTION_MASK_ISA2_AVX_UNSET \ > > > > > > + | OPTION_MASK_ISA2_AVX512F_UNSET) > > > > > > > > > > The above should only need OPTION_MASK_ISA2_SSE_UNSET, other options > > > > > follow from #define chain. > > > > > > > > > > > > > Here is the v2 patch to use OPTION_MASK_ISA2_SSE_UNSET. OK for > > > > master and GCC 11 branches? > > > > > > Have you regressiont tested it? > > > > I tested with the original patch. Since OPTION_MASK_ISA2_SSE_UNSET > > is the same as > > > > (OPTION_MASK_ISA2_SSE_UNSET > > | OPTION_MASK_ISA2_AVX_UNSET > > | OPTION_MASK_ISA2_AVX512F_UNSET) > > > > there should be no difference. > > I hope so. > > OK. I am backpoting this to GCC 11. > Thanks, > Uros. > > > > > > > > > > Thanks. > > > > > > > > > > > > H.J. > > > > --- > > > > Replace OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET > > > > in OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET to disable SSE, AVX and > > > > AVX512 ISAs. > > > > > > > > gcc/ > > > > > > > > PR target/105000 > > > > * common/config/i386/i386-common.cc > > > > (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace > > > > OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET. > > > > > > > > gcc/testsuite/ > > > > > > > > PR target/105000 > > > > * gcc.target/i386/pr105000-1.c: New test. > > > > * gcc.target/i386/pr105000-2.c: Likewise. > > > > * gcc.target/i386/pr105000-3.c: Likewise. > > > > * gcc.target/i386/pr105000-4.c: Likewise. > > > > --- > > > > gcc/common/config/i386/i386-common.cc | 2 +- > > > > gcc/testsuite/gcc.target/i386/pr105000-1.c | 11 +++++++++++ > > > > gcc/testsuite/gcc.target/i386/pr105000-2.c | 11 +++++++++++ > > > > gcc/testsuite/gcc.target/i386/pr105000-3.c | 11 +++++++++++ > > > > gcc/testsuite/gcc.target/i386/pr105000-4.c | 11 +++++++++++ > > > > 5 files changed, 45 insertions(+), 1 deletion(-) > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-1.c > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-2.c > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-3.c > > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-4.c > > > > > > > > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc > > > > index 449df6351c9..c64d7b01126 100644 > > > > --- a/gcc/common/config/i386/i386-common.cc > > > > +++ b/gcc/common/config/i386/i386-common.cc > > > > @@ -321,7 +321,7 @@ along with GCC; see the file COPYING3. If not see > > > > | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ > > > > | OPTION_MASK_ISA2_AVX512FP16_UNSET) > > > > #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ > > > > - (OPTION_MASK_ISA2_AVX512F_UNSET) > > > > + (OPTION_MASK_ISA2_SSE_UNSET) > > > > > > No need for parenthesis. > > > > > > > Fixed in the v3 patch. > > > > > > H.J. > > --- > > Replace OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET > > in OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET to disable SSE, AVX and > > AVX512 ISAs. > > > > gcc/ > > > > PR target/105000 > > * common/config/i386/i386-common.cc > > (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace > > OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET. > > > > gcc/testsuite/ > > > > PR target/105000 > > * gcc.target/i386/pr105000-1.c: New test. > > * gcc.target/i386/pr105000-2.c: Likewise. > > * gcc.target/i386/pr105000-3.c: Likewise. > > * gcc.target/i386/pr105000-4.c: Likewise. > > --- > > gcc/common/config/i386/i386-common.cc | 2 +- > > gcc/testsuite/gcc.target/i386/pr105000-1.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/i386/pr105000-2.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/i386/pr105000-3.c | 11 +++++++++++ > > gcc/testsuite/gcc.target/i386/pr105000-4.c | 11 +++++++++++ > > 5 files changed, 45 insertions(+), 1 deletion(-) > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-1.c > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-2.c > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-3.c > > create mode 100644 gcc/testsuite/gcc.target/i386/pr105000-4.c > > > > diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc > > index 449df6351c9..07fdd045f30 100644 > > --- a/gcc/common/config/i386/i386-common.cc > > +++ b/gcc/common/config/i386/i386-common.cc > > @@ -321,7 +321,7 @@ along with GCC; see the file COPYING3. If not see > > | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ > > | OPTION_MASK_ISA2_AVX512FP16_UNSET) > > #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ > > - (OPTION_MASK_ISA2_AVX512F_UNSET) > > + OPTION_MASK_ISA2_SSE_UNSET > > #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET > > #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET > > #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET > > diff --git a/gcc/testsuite/gcc.target/i386/pr105000-1.c b/gcc/testsuite/gcc.target/i386/pr105000-1.c > > new file mode 100644 > > index 00000000000..020e2adca83 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/i386/pr105000-1.c > > @@ -0,0 +1,11 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -mshstk -mavxvnni" } */ > > + > > +#include <x86gprintrin.h> > > + > > +__attribute__((target("no-mmx,no-sse"))) > > +int > > +foo () > > +{ > > + return _get_ssp (); > > +} > > diff --git a/gcc/testsuite/gcc.target/i386/pr105000-2.c b/gcc/testsuite/gcc.target/i386/pr105000-2.c > > new file mode 100644 > > index 00000000000..a113fd1dfa2 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/i386/pr105000-2.c > > @@ -0,0 +1,11 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -mshstk -mkl" } */ > > + > > +#include <x86gprintrin.h> > > + > > +__attribute__((target("no-mmx,no-sse"))) > > +int > > +foo () > > +{ > > + return _get_ssp (); > > +} > > diff --git a/gcc/testsuite/gcc.target/i386/pr105000-3.c b/gcc/testsuite/gcc.target/i386/pr105000-3.c > > new file mode 100644 > > index 00000000000..7e82925270c > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/i386/pr105000-3.c > > @@ -0,0 +1,11 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -mshstk -mwidekl" } */ > > + > > +#include <x86gprintrin.h> > > + > > +__attribute__((target("no-mmx,no-sse"))) > > +int > > +foo () > > +{ > > + return _get_ssp (); > > +} > > diff --git a/gcc/testsuite/gcc.target/i386/pr105000-4.c b/gcc/testsuite/gcc.target/i386/pr105000-4.c > > new file mode 100644 > > index 00000000000..195eabe85a2 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/i386/pr105000-4.c > > @@ -0,0 +1,11 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -mshstk -mavx512fp16" } */ > > + > > +#include <x86gprintrin.h> > > + > > +__attribute__((target("no-mmx,no-sse"))) > > +int > > +foo () > > +{ > > + return _get_ssp (); > > +} > > -- > > 2.35.1 > >
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 449df6351c9..07fdd045f30 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -321,7 +321,7 @@ along with GCC; see the file COPYING3. If not see | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ | OPTION_MASK_ISA2_AVX512FP16_UNSET) #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ - (OPTION_MASK_ISA2_AVX512F_UNSET) + OPTION_MASK_ISA2_SSE_UNSET #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET diff --git a/gcc/testsuite/gcc.target/i386/pr105000-1.c b/gcc/testsuite/gcc.target/i386/pr105000-1.c new file mode 100644 index 00000000000..020e2adca83 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105000-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mshstk -mavxvnni" } */ + +#include <x86gprintrin.h> + +__attribute__((target("no-mmx,no-sse"))) +int +foo () +{ + return _get_ssp (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr105000-2.c b/gcc/testsuite/gcc.target/i386/pr105000-2.c new file mode 100644 index 00000000000..a113fd1dfa2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105000-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mshstk -mkl" } */ + +#include <x86gprintrin.h> + +__attribute__((target("no-mmx,no-sse"))) +int +foo () +{ + return _get_ssp (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr105000-3.c b/gcc/testsuite/gcc.target/i386/pr105000-3.c new file mode 100644 index 00000000000..7e82925270c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105000-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mshstk -mwidekl" } */ + +#include <x86gprintrin.h> + +__attribute__((target("no-mmx,no-sse"))) +int +foo () +{ + return _get_ssp (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr105000-4.c b/gcc/testsuite/gcc.target/i386/pr105000-4.c new file mode 100644 index 00000000000..195eabe85a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105000-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mshstk -mavx512fp16" } */ + +#include <x86gprintrin.h> + +__attribute__((target("no-mmx,no-sse"))) +int +foo () +{ + return _get_ssp (); +}