===================================================================
@@ -659,9 +659,11 @@
(eq_attr "isa" "noavx2") (symbol_ref "!TARGET_AVX2")
(eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
(eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
- ;; Disable generation of FMA4 instructions for generic code
- ;; since FMA3 is preferred for targets that implement both
- ;; instruction sets.
+ ;; Fma instruction selection has to be done based on
+ ;; register pressure. For generating fma4, a cost model
+ ;; based on register pressure is required. Till then,
+ ;; fma4 instruction is disabled for targets that implement
+ ;; both fma and fma4 instruction sets.
(eq_attr "isa" "fma4")
(symbol_ref "TARGET_FMA4 && !TARGET_FMA")
]
===================================================================
@@ -483,8 +483,6 @@
has_abm = ecx & bit_ABM;
has_lwp = ecx & bit_LWP;
has_fma4 = ecx & bit_FMA4;
- if (vendor == SIG_AMD && has_fma4 && has_fma)
- has_fma4 = 0;
has_xop = ecx & bit_XOP;
has_tbm = ecx & bit_TBM;
has_lzcnt = ecx & bit_LZCNT;
===================================================================
@@ -3164,7 +3164,7 @@
{"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
+ | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
| PTA_FMA},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC64,