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|---|---|
| State | New |
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| Series | [v2,ARM,1/1x] : Patch to support MVE ACLE intrinsics with unary operand. | expand |
Hi Srinath,
Thanks, I've pushed this to master.
Kyrill
-----Original Message-----
From: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>
Sent: 10 March 2020 18:21
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
Subject: [PATCH v2][ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with unary operand.
Hello Kyrill,
Following patch is the rebased version of v1.
(version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-November/534343.html
####
Hello,
This patch supports MVE ACLE intrinsics vcvtq_f16_s16, vcvtq_f32_s32, vcvtq_f16_u16, vcvtq_f32_u32n vrndxq_f16, vrndxq_f32, vrndq_f16, vrndq_f32, vrndpq_f16, vrndpq_f32, vrndnq_f16, vrndnq_f32, vrndmq_f16, vrndmq_f32, vrndaq_f16, vrndaq_f32, vrev64q_f16, vrev64q_f32, vnegq_f16, vnegq_f32, vdupq_n_f16, vdupq_n_f32, vabsq_f16, vabsq_f32, vrev32q_f16, vcvttq_f32_f16, vcvtbq_f32_f16.
Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics
Regression tested on target arm-none-eabi and armeb-none-eabi and found no regressions.
Ok for trunk?
Thanks,
Srinath.
gcc/ChangeLog:
2020-03-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
(UNOP_NONE_SNONE_QUALIFIERS): Likewise.
(UNOP_NONE_UNONE_QUALIFIERS): Likewise.
* config/arm/arm_mve.h (vrndxq_f16): Define macro.
(vrndxq_f32): Likewise.
(vrndq_f16) Likewise.:
(vrndq_f32): Likewise.
(vrndpq_f16): Likewise.
(vrndpq_f32): Likewise.
(vrndnq_f16): Likewise.
(vrndnq_f32): Likewise.
(vrndmq_f16): Likewise.
(vrndmq_f32): Likewise.
(vrndaq_f16): Likewise.
(vrndaq_f32): Likewise.
(vrev64q_f16): Likewise.
(vrev64q_f32): Likewise.
(vnegq_f16): Likewise.
(vnegq_f32): Likewise.
(vdupq_n_f16): Likewise.
(vdupq_n_f32): Likewise.
(vabsq_f16): Likewise.
(vabsq_f32): Likewise.
(vrev32q_f16): Likewise.
(vcvttq_f32_f16): Likewise.
(vcvtbq_f32_f16): Likewise.
(vcvtq_f16_s16): Likewise.
(vcvtq_f32_s32): Likewise.
(vcvtq_f16_u16): Likewise.
(vcvtq_f32_u32): Likewise.
(__arm_vrndxq_f16): Define intrinsic.
(__arm_vrndxq_f32): Likewise.
(__arm_vrndq_f16): Likewise.
(__arm_vrndq_f32): Likewise.
(__arm_vrndpq_f16): Likewise.
(__arm_vrndpq_f32): Likewise.
(__arm_vrndnq_f16): Likewise.
(__arm_vrndnq_f32): Likewise.
(__arm_vrndmq_f16): Likewise.
(__arm_vrndmq_f32): Likewise.
(__arm_vrndaq_f16): Likewise.
(__arm_vrndaq_f32): Likewise.
(__arm_vrev64q_f16): Likewise.
(__arm_vrev64q_f32): Likewise.
(__arm_vnegq_f16): Likewise.
(__arm_vnegq_f32): Likewise.
(__arm_vdupq_n_f16): Likewise.
(__arm_vdupq_n_f32): Likewise.
(__arm_vabsq_f16): Likewise.
(__arm_vabsq_f32): Likewise.
(__arm_vrev32q_f16): Likewise.
(__arm_vcvttq_f32_f16): Likewise.
(__arm_vcvtbq_f32_f16): Likewise.
(__arm_vcvtq_f16_s16): Likewise.
(__arm_vcvtq_f32_s32): Likewise.
(__arm_vcvtq_f16_u16): Likewise.
(__arm_vcvtq_f32_u32): Likewise.
(vrndxq): Define polymorphic variants.
(vrndq): Likewise.
(vrndpq): Likewise.
(vrndnq): Likewise.
(vrndmq): Likewise.
(vrndaq): Likewise.
(vrev64q): Likewise.
(vnegq): Likewise.
(vabsq): Likewise.
(vrev32q): Likewise.
(vcvtbq_f32): Likewise.
(vcvttq_f32): Likewise.
(vcvtq): Likewise.
* config/arm/arm_mve_builtins.def (VAR2): Define.
(VAR1): Define.
* config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
(mve_vrndq_f<mode>): Likewise.
(mve_vrndpq_f<mode>): Likewise.
(mve_vrndnq_f<mode>): Likewise.
(mve_vrndmq_f<mode>): Likewise.
(mve_vrndaq_f<mode>): Likewise.
(mve_vrev64q_f<mode>): Likewise.
(mve_vnegq_f<mode>): Likewise.
(mve_vdupq_n_f<mode>): Likewise.
(mve_vabsq_f<mode>): Likewise.
(mve_vrev32q_fv8hf): Likewise.
(mve_vcvttq_f32_f16v4sf): Likewise.
(mve_vcvtbq_f32_f16v4sf): Likewise.
(mve_vcvtq_to_f_<supf><mode>): Likewise.
gcc/testsuite/ChangeLog:
2020-03-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise.
############### Attachment also inlined for ease of reply ###############
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b9ee45d5950ac9c1e12d88cd7d3ece1953dc51d0..11f32f16754001ff0f985e9e8c26127a9b7ef4ba 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -317,6 +317,28 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode, qualifier_none }; #define STORE1_QUALIFIERS (arm_store1_qualifiers)
+/* Qualifiers for MVE builtins. */
+
+static enum arm_type_qualifiers
+arm_unop_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_none }; #define
+UNOP_NONE_NONE_QUALIFIERS \
+ (arm_unop_none_none_qualifiers)
+
+static enum arm_type_qualifiers
+arm_unop_none_snone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_none }; #define
+UNOP_NONE_SNONE_QUALIFIERS \
+ (arm_unop_none_snone_qualifiers)
+
+static enum arm_type_qualifiers
+arm_unop_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_unsigned }; #define
+UNOP_NONE_UNONE_QUALIFIERS \
+ (arm_unop_none_unone_qualifiers)
+
+/* End of Qualifier for MVE builtins. */
+
/* void ([T element type] *, T, immediate). */ static enum arm_type_qualifiers arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 39c6a1551a72700292dde8ef6cea44ba0907af8d..9bcb04fb99a54b47057bb33cc807d6a5ad16401f 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -81,6 +81,33 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) #define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) #define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value)
+#define vrndxq_f16(__a) __arm_vrndxq_f16(__a) #define vrndxq_f32(__a)
+__arm_vrndxq_f32(__a) #define vrndq_f16(__a) __arm_vrndq_f16(__a)
+#define vrndq_f32(__a) __arm_vrndq_f32(__a) #define vrndpq_f16(__a)
+__arm_vrndpq_f16(__a) #define vrndpq_f32(__a) __arm_vrndpq_f32(__a)
+#define vrndnq_f16(__a) __arm_vrndnq_f16(__a) #define vrndnq_f32(__a)
+__arm_vrndnq_f32(__a) #define vrndmq_f16(__a) __arm_vrndmq_f16(__a)
+#define vrndmq_f32(__a) __arm_vrndmq_f32(__a) #define vrndaq_f16(__a)
+__arm_vrndaq_f16(__a) #define vrndaq_f32(__a) __arm_vrndaq_f32(__a)
+#define vrev64q_f16(__a) __arm_vrev64q_f16(__a) #define
+vrev64q_f32(__a) __arm_vrev64q_f32(__a) #define vnegq_f16(__a)
+__arm_vnegq_f16(__a) #define vnegq_f32(__a) __arm_vnegq_f32(__a)
+#define vdupq_n_f16(__a) __arm_vdupq_n_f16(__a) #define
+vdupq_n_f32(__a) __arm_vdupq_n_f32(__a) #define vabsq_f16(__a)
+__arm_vabsq_f16(__a) #define vabsq_f32(__a) __arm_vabsq_f32(__a)
+#define vrev32q_f16(__a) __arm_vrev32q_f16(__a) #define
+vcvttq_f32_f16(__a) __arm_vcvttq_f32_f16(__a) #define
+vcvtbq_f32_f16(__a) __arm_vcvtbq_f32_f16(__a) #define
+vcvtq_f16_s16(__a) __arm_vcvtq_f16_s16(__a) #define vcvtq_f32_s32(__a)
+__arm_vcvtq_f32_s32(__a) #define vcvtq_f16_u16(__a)
+__arm_vcvtq_f16_u16(__a) #define vcvtq_f32_u32(__a)
+__arm_vcvtq_f32_u32(__a)
#endif
__extension__ extern __inline void
@@ -157,6 +184,195 @@ __arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value)
__builtin_mve_vst4qv4sf (__addr, __rv.__o); }
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndxq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndxq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndxq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndxq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndpq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndpq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndpq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndpq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndnq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndnq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndnq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndnq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndmq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndmq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndmq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndmq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndaq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndaq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndaq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndaq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev64q_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrev64q_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev64q_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrev64q_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vnegq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vnegq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vnegq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vnegq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vdupq_n_f16 (float16_t __a)
+{
+ return __builtin_mve_vdupq_n_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vdupq_n_f32 (float32_t __a)
+{
+ return __builtin_mve_vdupq_n_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabsq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vabsq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabsq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vabsq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev32q_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrev32q_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvttq_f32_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvttq_f32_f16v4sf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtbq_f32_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtbq_f32_f16v4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f16_s16 (int16x8_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_sv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f32_s32 (int32x4_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_sv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f16_u16 (uint16x8_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_uv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f32_u32 (uint32x4_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_uv4sf (__a); }
+
#endif
enum {
@@ -368,6 +584,83 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \
int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));})
+#define vrndxq(p0) __arm_vrndxq(p0)
+#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndq(p0) __arm_vrndq(p0)
+#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndpq(p0) __arm_vrndpq(p0)
+#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndnq(p0) __arm_vrndnq(p0)
+#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndmq(p0) __arm_vrndmq(p0)
+#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndaq(p0) __arm_vrndaq(p0)
+#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrev64q(p0) __arm_vrev64q(p0)
+#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vnegq(p0) __arm_vnegq(p0)
+#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vabsq(p0) __arm_vabsq(p0)
+#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrev32q(p0) __arm_vrev32q(p0)
+#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16
+(__ARM_mve_coerce(__p0, float16x8_t)));})
+
+#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) #define
+__arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16
+(__ARM_mve_coerce(__p0, float16x8_t)));})
+
+#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) #define
+__arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16
+(__ARM_mve_coerce(__p0, float16x8_t)));})
+
+#define vcvtq(p0) __arm_vcvtq(p0)
+#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16
+(__ARM_mve_coerce(__p0, int16x8_t)), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32
+(__ARM_mve_coerce(__p0, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16
+(__ARM_mve_coerce(__p0, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32
+(__ARM_mve_coerce(__p0, uint32x4_t)));})
+
#else /* MVE Interger. */
#define vst4q(p0,p1) __arm_vst4q(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index c7f3546c9cb0ec3ae794e181e533a1cbed38121c..65dc58c9328525891a0aa0bb97a412ebc8257c18 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -19,3 +19,18 @@
<http://www.gnu.org/licenses/>. */
VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf)
+VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf)
+VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf)
+VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf)
+VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf)
+VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 9b3bb6129a99c4f3c952e7a72d0874dcba12f30d..e5f7e1d61da84e6cb608dd3d37dee6b12c76eea3 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -21,8 +21,18 @@
(V2DI "u64")])
(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
+(define_mode_iterator MVE_0 [V8HF V4SF])
-(define_c_enum "unspec" [VST4Q])
+(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
+ VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
+ VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S
+ VCVTQ_TO_F_U])
+
+(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
+ (V8HF "V8HI") (V4SF "V4SI")])
+
+(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")])
+(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -120,3 +130,198 @@
return "";
}
[(set_attr "length" "16")])
+
+;;
+;; [vrndxq_f])
+;;
+(define_insn "mve_vrndxq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDXQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintx.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndq_f])
+;;
+(define_insn "mve_vrndq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintz.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndpq_f])
+;;
+(define_insn "mve_vrndpq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDPQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintp.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndnq_f])
+;;
+(define_insn "mve_vrndnq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDNQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintn.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndmq_f])
+;;
+(define_insn "mve_vrndmq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDMQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintm.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndaq_f])
+;;
+(define_insn "mve_vrndaq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDAQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrinta.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrev64q_f])
+;;
+(define_insn "mve_vrev64q_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VREV64Q_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrev64.%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vnegq_f])
+;;
+(define_insn "mve_vnegq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VNEGQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vneg.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vdupq_n_f])
+;;
+(define_insn "mve_vdupq_n_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
+ VDUPQ_N_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vdup.%#<V_sz_elem> %q0, %1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vabsq_f])
+;;
+(define_insn "mve_vabsq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VABSQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vabs.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrev32q_f])
+;;
+(define_insn "mve_vrev32q_fv8hf"
+ [
+ (set (match_operand:V8HF 0 "s_register_operand" "=w")
+ (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
+ VREV32Q_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrev32.16 %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+;;
+;; [vcvttq_f32_f16])
+;;
+(define_insn "mve_vcvttq_f32_f16v4sf"
+ [
+ (set (match_operand:V4SF 0 "s_register_operand" "=w")
+ (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
+ VCVTTQ_F32_F16))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vcvtt.f32.f16 %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vcvtbq_f32_f16])
+;;
+(define_insn "mve_vcvtbq_f32_f16v4sf"
+ [
+ (set (match_operand:V4SF 0 "s_register_operand" "=w")
+ (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
+ VCVTBQ_F32_F16))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vcvtb.f32.f16 %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vcvtq_to_f_s, vcvtq_to_f_u])
+;;
+(define_insn "mve_vcvtq_to_f_<supf><mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
+ VCVTQ_TO_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..f49807cb863cb0bf7718e742692756d3a6a8311e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vabsq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vabs.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..ab44b314c3895a77d4c6a3591386a7ad300c95c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vabsq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vabs.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..bc57f261f2ca3d6b66e05553dc8069e88d9b8ba8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float16x8_t a)
+{
+ return vcvtbq_f32_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a7d9c2cf7eca3d1501cbf945625ab807b067558
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (int16x8_t a)
+{
+ return vcvtq_f16_s16 (a);
+}
+
+/* { dg-final { scan-assembler "vcvt.f16.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..6aae96862c4a389b25dba3cd194c73ebc1e7ee96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (uint16x8_t a)
+{
+ return vcvtq_f16_u16 (a);
+}
+
+/* { dg-final { scan-assembler "vcvt.f16.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..b563fe972bd08173ff3c2cadce975523d434d127
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (int32x4_t a)
+{
+ return vcvtq_f32_s32 (a);
+}
+
+/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..f5354a4a02faeab5d33798a3821e00838702eaa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (uint32x4_t a)
+{
+ return vcvtq_f32_u32 (a);
+}
+
+/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..2c0f4fda6be551651cb1fa631eb4a80dc8a75a3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float16x8_t a)
+{
+ return vcvttq_f32_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..616c24fd3aaf92603a207051f62af87a3b968769
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16_t a)
+{
+ return vdupq_n_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vdup.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..570dfde905f2858f6280474d99d7c01e28a320cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32_t a)
+{
+ return vdupq_n_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vdup.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..89d0162c274924199f5ef487232aaf0d057a1315
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vnegq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vneg.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..8cbdd16342da17151afafa80e493a217ec4c3c2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vnegq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vneg.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..86bf47dea54965aee76d7066188367c8bd1c109f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrev32q_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrev32.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..d7f75fd9d3dbb4c0cc2cad4c108d900c59b8b253
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrev64q_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrev64.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..131ec461b0ed0bd52cd474d4a9303a0717b95f36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrev64q_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrev64.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..d647d31ac705bce5265ecf8dd4230736d8306da4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndaq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrinta.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..4d5ba502bc57269a9395c3287ad7902fd570a788
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndaq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrinta.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..996b0b27c159114283fed2b5f62861ea93b38b15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndmq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintm.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..fae0a5ca2f15305d23d39b189ab0bb1a640618a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndmq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintm.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..cc00b6eb6131f726055a00bd3175fa1a637210f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndnq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintn.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..150e9d38342b68bc48a9d3d0c62c6d721e8876a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndnq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintn.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..d75ea35c02cef41133d8750a408d0a072c82fa1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndpq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintp.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..45de7fb5c591f4e481a575eb231d3e2758bb5dfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndpq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintp.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..b3a96540508fbe57999ea8d3a37b477ebb3b5193
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintz.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..c8a723ae4d7f79ff4c798962d14d80375da8faa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintz.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..aa364f0671fea913dfb421aab5731a2afb87d99b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndxq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintx.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..99a758110c7558fac5cbea522c33a8267a49aab1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndxq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintx.f32" } } */
Hi Srinath,
Thanks, I've pushed this to master.
Kyrill
-----Original Message-----
From: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>
Sent: 10 March 2020 18:21
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
Subject: [PATCH v2][ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with unary operand.
Hello Kyrill,
Following patch is the rebased version of v1.
(version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-November/534343.html
####
Hello,
This patch supports MVE ACLE intrinsics vcvtq_f16_s16, vcvtq_f32_s32, vcvtq_f16_u16, vcvtq_f32_u32n vrndxq_f16, vrndxq_f32, vrndq_f16, vrndq_f32, vrndpq_f16, vrndpq_f32, vrndnq_f16, vrndnq_f32, vrndmq_f16, vrndmq_f32, vrndaq_f16, vrndaq_f32, vrev64q_f16, vrev64q_f32, vnegq_f16, vnegq_f32, vdupq_n_f16, vdupq_n_f32, vabsq_f16, vabsq_f32, vrev32q_f16, vcvttq_f32_f16, vcvtbq_f32_f16.
Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics
Regression tested on target arm-none-eabi and armeb-none-eabi and found no regressions.
Ok for trunk?
Thanks,
Srinath.
gcc/ChangeLog:
2020-03-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
(UNOP_NONE_SNONE_QUALIFIERS): Likewise.
(UNOP_NONE_UNONE_QUALIFIERS): Likewise.
* config/arm/arm_mve.h (vrndxq_f16): Define macro.
(vrndxq_f32): Likewise.
(vrndq_f16) Likewise.:
(vrndq_f32): Likewise.
(vrndpq_f16): Likewise.
(vrndpq_f32): Likewise.
(vrndnq_f16): Likewise.
(vrndnq_f32): Likewise.
(vrndmq_f16): Likewise.
(vrndmq_f32): Likewise.
(vrndaq_f16): Likewise.
(vrndaq_f32): Likewise.
(vrev64q_f16): Likewise.
(vrev64q_f32): Likewise.
(vnegq_f16): Likewise.
(vnegq_f32): Likewise.
(vdupq_n_f16): Likewise.
(vdupq_n_f32): Likewise.
(vabsq_f16): Likewise.
(vabsq_f32): Likewise.
(vrev32q_f16): Likewise.
(vcvttq_f32_f16): Likewise.
(vcvtbq_f32_f16): Likewise.
(vcvtq_f16_s16): Likewise.
(vcvtq_f32_s32): Likewise.
(vcvtq_f16_u16): Likewise.
(vcvtq_f32_u32): Likewise.
(__arm_vrndxq_f16): Define intrinsic.
(__arm_vrndxq_f32): Likewise.
(__arm_vrndq_f16): Likewise.
(__arm_vrndq_f32): Likewise.
(__arm_vrndpq_f16): Likewise.
(__arm_vrndpq_f32): Likewise.
(__arm_vrndnq_f16): Likewise.
(__arm_vrndnq_f32): Likewise.
(__arm_vrndmq_f16): Likewise.
(__arm_vrndmq_f32): Likewise.
(__arm_vrndaq_f16): Likewise.
(__arm_vrndaq_f32): Likewise.
(__arm_vrev64q_f16): Likewise.
(__arm_vrev64q_f32): Likewise.
(__arm_vnegq_f16): Likewise.
(__arm_vnegq_f32): Likewise.
(__arm_vdupq_n_f16): Likewise.
(__arm_vdupq_n_f32): Likewise.
(__arm_vabsq_f16): Likewise.
(__arm_vabsq_f32): Likewise.
(__arm_vrev32q_f16): Likewise.
(__arm_vcvttq_f32_f16): Likewise.
(__arm_vcvtbq_f32_f16): Likewise.
(__arm_vcvtq_f16_s16): Likewise.
(__arm_vcvtq_f32_s32): Likewise.
(__arm_vcvtq_f16_u16): Likewise.
(__arm_vcvtq_f32_u32): Likewise.
(vrndxq): Define polymorphic variants.
(vrndq): Likewise.
(vrndpq): Likewise.
(vrndnq): Likewise.
(vrndmq): Likewise.
(vrndaq): Likewise.
(vrev64q): Likewise.
(vnegq): Likewise.
(vabsq): Likewise.
(vrev32q): Likewise.
(vcvtbq_f32): Likewise.
(vcvttq_f32): Likewise.
(vcvtq): Likewise.
* config/arm/arm_mve_builtins.def (VAR2): Define.
(VAR1): Define.
* config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
(mve_vrndq_f<mode>): Likewise.
(mve_vrndpq_f<mode>): Likewise.
(mve_vrndnq_f<mode>): Likewise.
(mve_vrndmq_f<mode>): Likewise.
(mve_vrndaq_f<mode>): Likewise.
(mve_vrev64q_f<mode>): Likewise.
(mve_vnegq_f<mode>): Likewise.
(mve_vdupq_n_f<mode>): Likewise.
(mve_vabsq_f<mode>): Likewise.
(mve_vrev32q_fv8hf): Likewise.
(mve_vcvttq_f32_f16v4sf): Likewise.
(mve_vcvtbq_f32_f16v4sf): Likewise.
(mve_vcvtq_to_f_<supf><mode>): Likewise.
gcc/testsuite/ChangeLog:
2020-03-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise.
############### Attachment also inlined for ease of reply ###############
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b9ee45d5950ac9c1e12d88cd7d3ece1953dc51d0..11f32f16754001ff0f985e9e8c26127a9b7ef4ba 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -317,6 +317,28 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode, qualifier_none }; #define STORE1_QUALIFIERS (arm_store1_qualifiers)
+/* Qualifiers for MVE builtins. */
+
+static enum arm_type_qualifiers
+arm_unop_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_none }; #define
+UNOP_NONE_NONE_QUALIFIERS \
+ (arm_unop_none_none_qualifiers)
+
+static enum arm_type_qualifiers
+arm_unop_none_snone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_none }; #define
+UNOP_NONE_SNONE_QUALIFIERS \
+ (arm_unop_none_snone_qualifiers)
+
+static enum arm_type_qualifiers
+arm_unop_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_unsigned }; #define
+UNOP_NONE_UNONE_QUALIFIERS \
+ (arm_unop_none_unone_qualifiers)
+
+/* End of Qualifier for MVE builtins. */
+
/* void ([T element type] *, T, immediate). */ static enum arm_type_qualifiers arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 39c6a1551a72700292dde8ef6cea44ba0907af8d..9bcb04fb99a54b47057bb33cc807d6a5ad16401f 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -81,6 +81,33 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) #define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) #define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value)
+#define vrndxq_f16(__a) __arm_vrndxq_f16(__a) #define vrndxq_f32(__a)
+__arm_vrndxq_f32(__a) #define vrndq_f16(__a) __arm_vrndq_f16(__a)
+#define vrndq_f32(__a) __arm_vrndq_f32(__a) #define vrndpq_f16(__a)
+__arm_vrndpq_f16(__a) #define vrndpq_f32(__a) __arm_vrndpq_f32(__a)
+#define vrndnq_f16(__a) __arm_vrndnq_f16(__a) #define vrndnq_f32(__a)
+__arm_vrndnq_f32(__a) #define vrndmq_f16(__a) __arm_vrndmq_f16(__a)
+#define vrndmq_f32(__a) __arm_vrndmq_f32(__a) #define vrndaq_f16(__a)
+__arm_vrndaq_f16(__a) #define vrndaq_f32(__a) __arm_vrndaq_f32(__a)
+#define vrev64q_f16(__a) __arm_vrev64q_f16(__a) #define
+vrev64q_f32(__a) __arm_vrev64q_f32(__a) #define vnegq_f16(__a)
+__arm_vnegq_f16(__a) #define vnegq_f32(__a) __arm_vnegq_f32(__a)
+#define vdupq_n_f16(__a) __arm_vdupq_n_f16(__a) #define
+vdupq_n_f32(__a) __arm_vdupq_n_f32(__a) #define vabsq_f16(__a)
+__arm_vabsq_f16(__a) #define vabsq_f32(__a) __arm_vabsq_f32(__a)
+#define vrev32q_f16(__a) __arm_vrev32q_f16(__a) #define
+vcvttq_f32_f16(__a) __arm_vcvttq_f32_f16(__a) #define
+vcvtbq_f32_f16(__a) __arm_vcvtbq_f32_f16(__a) #define
+vcvtq_f16_s16(__a) __arm_vcvtq_f16_s16(__a) #define vcvtq_f32_s32(__a)
+__arm_vcvtq_f32_s32(__a) #define vcvtq_f16_u16(__a)
+__arm_vcvtq_f16_u16(__a) #define vcvtq_f32_u32(__a)
+__arm_vcvtq_f32_u32(__a)
#endif
__extension__ extern __inline void
@@ -157,6 +184,195 @@ __arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value)
__builtin_mve_vst4qv4sf (__addr, __rv.__o); }
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndxq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndxq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndxq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndxq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndpq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndpq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndpq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndpq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndnq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndnq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndnq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndnq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndmq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndmq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndmq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndmq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndaq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndaq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndaq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrndaq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev64q_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrev64q_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev64q_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vrev64q_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vnegq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vnegq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vnegq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vnegq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vdupq_n_f16 (float16_t __a)
+{
+ return __builtin_mve_vdupq_n_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vdupq_n_f32 (float32_t __a)
+{
+ return __builtin_mve_vdupq_n_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabsq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vabsq_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabsq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vabsq_fv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev32q_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrev32q_fv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvttq_f32_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvttq_f32_f16v4sf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtbq_f32_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtbq_f32_f16v4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f16_s16 (int16x8_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_sv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f32_s32 (int32x4_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_sv4sf (__a); }
+
+__extension__ extern __inline float16x8_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f16_u16 (uint16x8_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_uv8hf (__a); }
+
+__extension__ extern __inline float32x4_t __attribute__
+((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f32_u32 (uint32x4_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_uv4sf (__a); }
+
#endif
enum {
@@ -368,6 +584,83 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \
int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));})
+#define vrndxq(p0) __arm_vrndxq(p0)
+#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndq(p0) __arm_vrndq(p0)
+#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndpq(p0) __arm_vrndpq(p0)
+#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndnq(p0) __arm_vrndnq(p0)
+#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndmq(p0) __arm_vrndmq(p0)
+#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrndaq(p0) __arm_vrndaq(p0)
+#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrev64q(p0) __arm_vrev64q(p0)
+#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vnegq(p0) __arm_vnegq(p0)
+#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vabsq(p0) __arm_vabsq(p0)
+#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16
+(__ARM_mve_coerce(__p0, float16x8_t)), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32
+(__ARM_mve_coerce(__p0, float32x4_t)));})
+
+#define vrev32q(p0) __arm_vrev32q(p0)
+#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16
+(__ARM_mve_coerce(__p0, float16x8_t)));})
+
+#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) #define
+__arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16
+(__ARM_mve_coerce(__p0, float16x8_t)));})
+
+#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) #define
+__arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16
+(__ARM_mve_coerce(__p0, float16x8_t)));})
+
+#define vcvtq(p0) __arm_vcvtq(p0)
+#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16
+(__ARM_mve_coerce(__p0, int16x8_t)), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32
+(__ARM_mve_coerce(__p0, int32x4_t)), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16
+(__ARM_mve_coerce(__p0, uint16x8_t)), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32
+(__ARM_mve_coerce(__p0, uint32x4_t)));})
+
#else /* MVE Interger. */
#define vst4q(p0,p1) __arm_vst4q(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index c7f3546c9cb0ec3ae794e181e533a1cbed38121c..65dc58c9328525891a0aa0bb97a412ebc8257c18 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -19,3 +19,18 @@
<http://www.gnu.org/licenses/>. */
VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf)
+VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf)
+VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf)
+VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf)
+VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf)
+VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf)
+VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 9b3bb6129a99c4f3c952e7a72d0874dcba12f30d..e5f7e1d61da84e6cb608dd3d37dee6b12c76eea3 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -21,8 +21,18 @@
(V2DI "u64")])
(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
+(define_mode_iterator MVE_0 [V8HF V4SF])
-(define_c_enum "unspec" [VST4Q])
+(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F
+ VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F
+ VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S
+ VCVTQ_TO_F_U])
+
+(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
+ (V8HF "V8HI") (V4SF "V4SI")])
+
+(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")])
+(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -120,3 +130,198 @@
return "";
}
[(set_attr "length" "16")])
+
+;;
+;; [vrndxq_f])
+;;
+(define_insn "mve_vrndxq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDXQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintx.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndq_f])
+;;
+(define_insn "mve_vrndq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintz.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndpq_f])
+;;
+(define_insn "mve_vrndpq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDPQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintp.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndnq_f])
+;;
+(define_insn "mve_vrndnq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDNQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintn.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndmq_f])
+;;
+(define_insn "mve_vrndmq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDMQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrintm.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrndaq_f])
+;;
+(define_insn "mve_vrndaq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VRNDAQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrinta.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrev64q_f])
+;;
+(define_insn "mve_vrev64q_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VREV64Q_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrev64.%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vnegq_f])
+;;
+(define_insn "mve_vnegq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VNEGQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vneg.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vdupq_n_f])
+;;
+(define_insn "mve_vdupq_n_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
+ VDUPQ_N_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vdup.%#<V_sz_elem> %q0, %1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vabsq_f])
+;;
+(define_insn "mve_vabsq_f<mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
+ VABSQ_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vabs.f%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vrev32q_f])
+;;
+(define_insn "mve_vrev32q_fv8hf"
+ [
+ (set (match_operand:V8HF 0 "s_register_operand" "=w")
+ (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")]
+ VREV32Q_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vrev32.16 %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+;;
+;; [vcvttq_f32_f16])
+;;
+(define_insn "mve_vcvttq_f32_f16v4sf"
+ [
+ (set (match_operand:V4SF 0 "s_register_operand" "=w")
+ (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
+ VCVTTQ_F32_F16))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vcvtt.f32.f16 %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vcvtbq_f32_f16])
+;;
+(define_insn "mve_vcvtbq_f32_f16v4sf"
+ [
+ (set (match_operand:V4SF 0 "s_register_operand" "=w")
+ (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
+ VCVTBQ_F32_F16))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vcvtb.f32.f16 %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vcvtq_to_f_s, vcvtq_to_f_u])
+;;
+(define_insn "mve_vcvtq_to_f_<supf><mode>"
+ [
+ (set (match_operand:MVE_0 0 "s_register_operand" "=w")
+ (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
+ VCVTQ_TO_F))
+ ]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+ "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1"
+ [(set_attr "type" "mve_move")
+])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..f49807cb863cb0bf7718e742692756d3a6a8311e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vabsq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vabs.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..ab44b314c3895a77d4c6a3591386a7ad300c95c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vabsq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vabs.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..bc57f261f2ca3d6b66e05553dc8069e88d9b8ba8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float16x8_t a)
+{
+ return vcvtbq_f32_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a7d9c2cf7eca3d1501cbf945625ab807b067558
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (int16x8_t a)
+{
+ return vcvtq_f16_s16 (a);
+}
+
+/* { dg-final { scan-assembler "vcvt.f16.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
new file mode 100644
index 0000000000000000000000000000000000000000..6aae96862c4a389b25dba3cd194c73ebc1e7ee96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (uint16x8_t a)
+{
+ return vcvtq_f16_u16 (a);
+}
+
+/* { dg-final { scan-assembler "vcvt.f16.u16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
new file mode 100644
index 0000000000000000000000000000000000000000..b563fe972bd08173ff3c2cadce975523d434d127
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (int32x4_t a)
+{
+ return vcvtq_f32_s32 (a);
+}
+
+/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
new file mode 100644
index 0000000000000000000000000000000000000000..f5354a4a02faeab5d33798a3821e00838702eaa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (uint32x4_t a)
+{
+ return vcvtq_f32_u32 (a);
+}
+
+/* { dg-final { scan-assembler "vcvt.f32.u32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..2c0f4fda6be551651cb1fa631eb4a80dc8a75a3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float16x8_t a)
+{
+ return vcvttq_f32_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..616c24fd3aaf92603a207051f62af87a3b968769
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16_t a)
+{
+ return vdupq_n_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vdup.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..570dfde905f2858f6280474d99d7c01e28a320cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32_t a)
+{
+ return vdupq_n_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vdup.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..89d0162c274924199f5ef487232aaf0d057a1315
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vnegq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vneg.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..8cbdd16342da17151afafa80e493a217ec4c3c2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vnegq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vneg.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..86bf47dea54965aee76d7066188367c8bd1c109f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrev32q_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrev32.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..d7f75fd9d3dbb4c0cc2cad4c108d900c59b8b253
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrev64q_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrev64.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..131ec461b0ed0bd52cd474d4a9303a0717b95f36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrev64q_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrev64.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..d647d31ac705bce5265ecf8dd4230736d8306da4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndaq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrinta.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..4d5ba502bc57269a9395c3287ad7902fd570a788
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndaq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrinta.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..996b0b27c159114283fed2b5f62861ea93b38b15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndmq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintm.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..fae0a5ca2f15305d23d39b189ab0bb1a640618a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndmq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintm.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..cc00b6eb6131f726055a00bd3175fa1a637210f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndnq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintn.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..150e9d38342b68bc48a9d3d0c62c6d721e8876a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndnq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintn.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..d75ea35c02cef41133d8750a408d0a072c82fa1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndpq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintp.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..45de7fb5c591f4e481a575eb231d3e2758bb5dfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndpq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintp.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..b3a96540508fbe57999ea8d3a37b477ebb3b5193
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintz.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..c8a723ae4d7f79ff4c798962d14d80375da8faa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintz.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
new file mode 100644
index 0000000000000000000000000000000000000000..aa364f0671fea913dfb421aab5731a2afb87d99b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a)
+{
+ return vrndxq_f16 (a);
+}
+
+/* { dg-final { scan-assembler "vrintx.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
new file mode 100644
index 0000000000000000000000000000000000000000..99a758110c7558fac5cbea522c33a8267a49aab1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a)
+{
+ return vrndxq_f32 (a);
+}
+
+/* { dg-final { scan-assembler "vrintx.f32" } } */
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b9ee45d5950ac9c1e12d88cd7d3ece1953dc51d0..11f32f16754001ff0f985e9e8c26127a9b7ef4ba 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -317,6 +317,28 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer_map_mode, qualifier_none }; #define STORE1_QUALIFIERS (arm_store1_qualifiers) +/* Qualifiers for MVE builtins. */ + +static enum arm_type_qualifiers +arm_unop_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_NONE_NONE_QUALIFIERS \ + (arm_unop_none_none_qualifiers) + +static enum arm_type_qualifiers +arm_unop_none_snone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_NONE_SNONE_QUALIFIERS \ + (arm_unop_none_snone_qualifiers) + +static enum arm_type_qualifiers +arm_unop_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned }; +#define UNOP_NONE_UNONE_QUALIFIERS \ + (arm_unop_none_unone_qualifiers) + +/* End of Qualifier for MVE builtins. */ + /* void ([T element type] *, T, immediate). */ static enum arm_type_qualifiers arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 39c6a1551a72700292dde8ef6cea44ba0907af8d..9bcb04fb99a54b47057bb33cc807d6a5ad16401f 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -81,6 +81,33 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) #define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) #define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value) +#define vrndxq_f16(__a) __arm_vrndxq_f16(__a) +#define vrndxq_f32(__a) __arm_vrndxq_f32(__a) +#define vrndq_f16(__a) __arm_vrndq_f16(__a) +#define vrndq_f32(__a) __arm_vrndq_f32(__a) +#define vrndpq_f16(__a) __arm_vrndpq_f16(__a) +#define vrndpq_f32(__a) __arm_vrndpq_f32(__a) +#define vrndnq_f16(__a) __arm_vrndnq_f16(__a) +#define vrndnq_f32(__a) __arm_vrndnq_f32(__a) +#define vrndmq_f16(__a) __arm_vrndmq_f16(__a) +#define vrndmq_f32(__a) __arm_vrndmq_f32(__a) +#define vrndaq_f16(__a) __arm_vrndaq_f16(__a) +#define vrndaq_f32(__a) __arm_vrndaq_f32(__a) +#define vrev64q_f16(__a) __arm_vrev64q_f16(__a) +#define vrev64q_f32(__a) __arm_vrev64q_f32(__a) +#define vnegq_f16(__a) __arm_vnegq_f16(__a) +#define vnegq_f32(__a) __arm_vnegq_f32(__a) +#define vdupq_n_f16(__a) __arm_vdupq_n_f16(__a) +#define vdupq_n_f32(__a) __arm_vdupq_n_f32(__a) +#define vabsq_f16(__a) __arm_vabsq_f16(__a) +#define vabsq_f32(__a) __arm_vabsq_f32(__a) +#define vrev32q_f16(__a) __arm_vrev32q_f16(__a) +#define vcvttq_f32_f16(__a) __arm_vcvttq_f32_f16(__a) +#define vcvtbq_f32_f16(__a) __arm_vcvtbq_f32_f16(__a) +#define vcvtq_f16_s16(__a) __arm_vcvtq_f16_s16(__a) +#define vcvtq_f32_s32(__a) __arm_vcvtq_f32_s32(__a) +#define vcvtq_f16_u16(__a) __arm_vcvtq_f16_u16(__a) +#define vcvtq_f32_u32(__a) __arm_vcvtq_f32_u32(__a) #endif __extension__ extern __inline void @@ -157,6 +184,195 @@ __arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) __builtin_mve_vst4qv4sf (__addr, __rv.__o); } +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndxq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndxq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndpq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndpq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndnq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndnq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndmq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndmq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndaq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndaq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev64q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f32 (float32x4_t __a) +{ + return __builtin_mve_vrev64q_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f16 (float16x8_t __a) +{ + return __builtin_mve_vnegq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f32 (float32x4_t __a) +{ + return __builtin_mve_vnegq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f16 (float16_t __a) +{ + return __builtin_mve_vdupq_n_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f32 (float32_t __a) +{ + return __builtin_mve_vdupq_n_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f16 (float16x8_t __a) +{ + return __builtin_mve_vabsq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f32 (float32x4_t __a) +{ + return __builtin_mve_vabsq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev32q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvttq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtbq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_s16 (int16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_s32 (int32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_u16 (uint16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_u32 (uint32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv4sf (__a); +} + #endif enum { @@ -368,6 +584,83 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) +#define vrndxq(p0) __arm_vrndxq(p0) +#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndq(p0) __arm_vrndq(p0) +#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndpq(p0) __arm_vrndpq(p0) +#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndnq(p0) __arm_vrndnq(p0) +#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndmq(p0) __arm_vrndmq(p0) +#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndaq(p0) __arm_vrndaq(p0) +#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev64q(p0) __arm_vrev64q(p0) +#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vnegq(p0) __arm_vnegq(p0) +#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vabsq(p0) __arm_vabsq(p0) +#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev32q(p0) __arm_vrev32q(p0) +#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) +#define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) +#define __arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtq(p0) __arm_vcvtq(p0) +#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + #else /* MVE Interger. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index c7f3546c9cb0ec3ae794e181e533a1cbed38121c..65dc58c9328525891a0aa0bb97a412ebc8257c18 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -19,3 +19,18 @@ <http://www.gnu.org/licenses/>. */ VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf) +VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf) +VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) +VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) +VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) +VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 9b3bb6129a99c4f3c952e7a72d0874dcba12f30d..e5f7e1d61da84e6cb608dd3d37dee6b12c76eea3 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -21,8 +21,18 @@ (V2DI "u64")]) (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) +(define_mode_iterator MVE_0 [V8HF V4SF]) -(define_c_enum "unspec" [VST4Q]) +(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F + VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F + VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S + VCVTQ_TO_F_U]) + +(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") + (V8HF "V8HI") (V4SF "V4SI")]) + +(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")]) +(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_insn "*mve_mov<mode>" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -120,3 +130,198 @@ return ""; } [(set_attr "length" "16")]) + +;; +;; [vrndxq_f]) +;; +(define_insn "mve_vrndxq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDXQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintx.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndq_f]) +;; +(define_insn "mve_vrndq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintz.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndpq_f]) +;; +(define_insn "mve_vrndpq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDPQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintp.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndnq_f]) +;; +(define_insn "mve_vrndnq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDNQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintn.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndmq_f]) +;; +(define_insn "mve_vrndmq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDMQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintm.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndaq_f]) +;; +(define_insn "mve_vrndaq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDAQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrinta.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev64q_f]) +;; +(define_insn "mve_vrev64q_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VREV64Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrev64.%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vnegq_f]) +;; +(define_insn "mve_vnegq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VNEGQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vneg.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vdupq_n_f]) +;; +(define_insn "mve_vdupq_n_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")] + VDUPQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vdup.%#<V_sz_elem> %q0, %1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vabsq_f]) +;; +(define_insn "mve_vabsq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VABSQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vabs.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev32q_f]) +;; +(define_insn "mve_vrev32q_fv8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")] + VREV32Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrev32.16 %q0, %q1" + [(set_attr "type" "mve_move") +]) +;; +;; [vcvttq_f32_f16]) +;; +(define_insn "mve_vcvttq_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] + VCVTTQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtt.f32.f16 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtbq_f32_f16]) +;; +(define_insn "mve_vcvtbq_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] + VCVTBQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtb.f32.f16 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtq_to_f_s, vcvtq_to_f_u]) +;; +(define_insn "mve_vcvtq_to_f_<supf><mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] + VCVTQ_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..f49807cb863cb0bf7718e742692756d3a6a8311e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vabsq_f16 (a); +} + +/* { dg-final { scan-assembler "vabs.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..ab44b314c3895a77d4c6a3591386a7ad300c95c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vabsq_f32 (a); +} + +/* { dg-final { scan-assembler "vabs.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..bc57f261f2ca3d6b66e05553dc8069e88d9b8ba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a) +{ + return vcvtbq_f32_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..9a7d9c2cf7eca3d1501cbf945625ab807b067558 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (int16x8_t a) +{ + return vcvtq_f16_s16 (a); +} + +/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..6aae96862c4a389b25dba3cd194c73ebc1e7ee96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (uint16x8_t a) +{ + return vcvtq_f16_u16 (a); +} + +/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..b563fe972bd08173ff3c2cadce975523d434d127 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (int32x4_t a) +{ + return vcvtq_f32_s32 (a); +} + +/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..f5354a4a02faeab5d33798a3821e00838702eaa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t a) +{ + return vcvtq_f32_u32 (a); +} + +/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..2c0f4fda6be551651cb1fa631eb4a80dc8a75a3b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a) +{ + return vcvttq_f32_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..616c24fd3aaf92603a207051f62af87a3b968769 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t a) +{ + return vdupq_n_f16 (a); +} + +/* { dg-final { scan-assembler "vdup.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..570dfde905f2858f6280474d99d7c01e28a320cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t a) +{ + return vdupq_n_f32 (a); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..89d0162c274924199f5ef487232aaf0d057a1315 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vnegq_f16 (a); +} + +/* { dg-final { scan-assembler "vneg.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..8cbdd16342da17151afafa80e493a217ec4c3c2a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vnegq_f32 (a); +} + +/* { dg-final { scan-assembler "vneg.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..86bf47dea54965aee76d7066188367c8bd1c109f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrev32q_f16 (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..d7f75fd9d3dbb4c0cc2cad4c108d900c59b8b253 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrev64q_f16 (a); +} + +/* { dg-final { scan-assembler "vrev64.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..131ec461b0ed0bd52cd474d4a9303a0717b95f36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrev64q_f32 (a); +} + +/* { dg-final { scan-assembler "vrev64.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..d647d31ac705bce5265ecf8dd4230736d8306da4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndaq_f16 (a); +} + +/* { dg-final { scan-assembler "vrinta.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..4d5ba502bc57269a9395c3287ad7902fd570a788 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndaq_f32 (a); +} + +/* { dg-final { scan-assembler "vrinta.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..996b0b27c159114283fed2b5f62861ea93b38b15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndmq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintm.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..fae0a5ca2f15305d23d39b189ab0bb1a640618a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndmq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintm.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..cc00b6eb6131f726055a00bd3175fa1a637210f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndnq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintn.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..150e9d38342b68bc48a9d3d0c62c6d721e8876a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndnq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintn.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..d75ea35c02cef41133d8750a408d0a072c82fa1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndpq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..45de7fb5c591f4e481a575eb231d3e2758bb5dfa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndpq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..b3a96540508fbe57999ea8d3a37b477ebb3b5193 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintz.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..c8a723ae4d7f79ff4c798962d14d80375da8faa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintz.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..aa364f0671fea913dfb421aab5731a2afb87d99b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndxq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintx.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..99a758110c7558fac5cbea522c33a8267a49aab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndxq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintx.f32" } } */
Hello Kyrill, Following patch is the rebased version of v1. (version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-November/534343.html #### Hello, This patch supports MVE ACLE intrinsics vcvtq_f16_s16, vcvtq_f32_s32, vcvtq_f16_u16, vcvtq_f32_u32n vrndxq_f16, vrndxq_f32, vrndq_f16, vrndq_f32, vrndpq_f16, vrndpq_f32, vrndnq_f16, vrndnq_f32, vrndmq_f16, vrndmq_f32, vrndaq_f16, vrndaq_f32, vrev64q_f16, vrev64q_f32, vnegq_f16, vnegq_f32, vdupq_n_f16, vdupq_n_f32, vabsq_f16, vabsq_f32, vrev32q_f16, vcvttq_f32_f16, vcvtbq_f32_f16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on target arm-none-eabi and armeb-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2020-03-06 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. (UNOP_NONE_SNONE_QUALIFIERS): Likewise. (UNOP_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vrndxq_f16): Define macro. (vrndxq_f32): Likewise. (vrndq_f16) Likewise.: (vrndq_f32): Likewise. (vrndpq_f16): Likewise. (vrndpq_f32): Likewise. (vrndnq_f16): Likewise. (vrndnq_f32): Likewise. (vrndmq_f16): Likewise. (vrndmq_f32): Likewise. (vrndaq_f16): Likewise. (vrndaq_f32): Likewise. (vrev64q_f16): Likewise. (vrev64q_f32): Likewise. (vnegq_f16): Likewise. (vnegq_f32): Likewise. (vdupq_n_f16): Likewise. (vdupq_n_f32): Likewise. (vabsq_f16): Likewise. (vabsq_f32): Likewise. (vrev32q_f16): Likewise. (vcvttq_f32_f16): Likewise. (vcvtbq_f32_f16): Likewise. (vcvtq_f16_s16): Likewise. (vcvtq_f32_s32): Likewise. (vcvtq_f16_u16): Likewise. (vcvtq_f32_u32): Likewise. (__arm_vrndxq_f16): Define intrinsic. (__arm_vrndxq_f32): Likewise. (__arm_vrndq_f16): Likewise. (__arm_vrndq_f32): Likewise. (__arm_vrndpq_f16): Likewise. (__arm_vrndpq_f32): Likewise. (__arm_vrndnq_f16): Likewise. (__arm_vrndnq_f32): Likewise. (__arm_vrndmq_f16): Likewise. (__arm_vrndmq_f32): Likewise. (__arm_vrndaq_f16): Likewise. (__arm_vrndaq_f32): Likewise. (__arm_vrev64q_f16): Likewise. (__arm_vrev64q_f32): Likewise. (__arm_vnegq_f16): Likewise. (__arm_vnegq_f32): Likewise. (__arm_vdupq_n_f16): Likewise. (__arm_vdupq_n_f32): Likewise. (__arm_vabsq_f16): Likewise. (__arm_vabsq_f32): Likewise. (__arm_vrev32q_f16): Likewise. (__arm_vcvttq_f32_f16): Likewise. (__arm_vcvtbq_f32_f16): Likewise. (__arm_vcvtq_f16_s16): Likewise. (__arm_vcvtq_f32_s32): Likewise. (__arm_vcvtq_f16_u16): Likewise. (__arm_vcvtq_f32_u32): Likewise. (vrndxq): Define polymorphic variants. (vrndq): Likewise. (vrndpq): Likewise. (vrndnq): Likewise. (vrndmq): Likewise. (vrndaq): Likewise. (vrev64q): Likewise. (vnegq): Likewise. (vabsq): Likewise. (vrev32q): Likewise. (vcvtbq_f32): Likewise. (vcvttq_f32): Likewise. (vcvtq): Likewise. * config/arm/arm_mve_builtins.def (VAR2): Define. (VAR1): Define. * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern. (mve_vrndq_f<mode>): Likewise. (mve_vrndpq_f<mode>): Likewise. (mve_vrndnq_f<mode>): Likewise. (mve_vrndmq_f<mode>): Likewise. (mve_vrndaq_f<mode>): Likewise. (mve_vrev64q_f<mode>): Likewise. (mve_vnegq_f<mode>): Likewise. (mve_vdupq_n_f<mode>): Likewise. (mve_vabsq_f<mode>): Likewise. (mve_vrev32q_fv8hf): Likewise. (mve_vcvttq_f32_f16v4sf): Likewise. (mve_vcvtbq_f32_f16v4sf): Likewise. (mve_vcvtq_to_f_<supf><mode>): Likewise. gcc/testsuite/ChangeLog: 2020-03-06 Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise. ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b9ee45d5950ac9c1e12d88cd7d3ece1953dc51d0..11f32f16754001ff0f985e9e8c26127a9b7ef4ba 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -317,6 +317,28 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer_map_mode, qualifier_none }; #define STORE1_QUALIFIERS (arm_store1_qualifiers) +/* Qualifiers for MVE builtins. */ + +static enum arm_type_qualifiers +arm_unop_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_NONE_NONE_QUALIFIERS \ + (arm_unop_none_none_qualifiers) + +static enum arm_type_qualifiers +arm_unop_none_snone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_NONE_SNONE_QUALIFIERS \ + (arm_unop_none_snone_qualifiers) + +static enum arm_type_qualifiers +arm_unop_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned }; +#define UNOP_NONE_UNONE_QUALIFIERS \ + (arm_unop_none_unone_qualifiers) + +/* End of Qualifier for MVE builtins. */ + /* void ([T element type] *, T, immediate). */ static enum arm_type_qualifiers arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 39c6a1551a72700292dde8ef6cea44ba0907af8d..9bcb04fb99a54b47057bb33cc807d6a5ad16401f 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -81,6 +81,33 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) #define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) #define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value) +#define vrndxq_f16(__a) __arm_vrndxq_f16(__a) +#define vrndxq_f32(__a) __arm_vrndxq_f32(__a) +#define vrndq_f16(__a) __arm_vrndq_f16(__a) +#define vrndq_f32(__a) __arm_vrndq_f32(__a) +#define vrndpq_f16(__a) __arm_vrndpq_f16(__a) +#define vrndpq_f32(__a) __arm_vrndpq_f32(__a) +#define vrndnq_f16(__a) __arm_vrndnq_f16(__a) +#define vrndnq_f32(__a) __arm_vrndnq_f32(__a) +#define vrndmq_f16(__a) __arm_vrndmq_f16(__a) +#define vrndmq_f32(__a) __arm_vrndmq_f32(__a) +#define vrndaq_f16(__a) __arm_vrndaq_f16(__a) +#define vrndaq_f32(__a) __arm_vrndaq_f32(__a) +#define vrev64q_f16(__a) __arm_vrev64q_f16(__a) +#define vrev64q_f32(__a) __arm_vrev64q_f32(__a) +#define vnegq_f16(__a) __arm_vnegq_f16(__a) +#define vnegq_f32(__a) __arm_vnegq_f32(__a) +#define vdupq_n_f16(__a) __arm_vdupq_n_f16(__a) +#define vdupq_n_f32(__a) __arm_vdupq_n_f32(__a) +#define vabsq_f16(__a) __arm_vabsq_f16(__a) +#define vabsq_f32(__a) __arm_vabsq_f32(__a) +#define vrev32q_f16(__a) __arm_vrev32q_f16(__a) +#define vcvttq_f32_f16(__a) __arm_vcvttq_f32_f16(__a) +#define vcvtbq_f32_f16(__a) __arm_vcvtbq_f32_f16(__a) +#define vcvtq_f16_s16(__a) __arm_vcvtq_f16_s16(__a) +#define vcvtq_f32_s32(__a) __arm_vcvtq_f32_s32(__a) +#define vcvtq_f16_u16(__a) __arm_vcvtq_f16_u16(__a) +#define vcvtq_f32_u32(__a) __arm_vcvtq_f32_u32(__a) #endif __extension__ extern __inline void @@ -157,6 +184,195 @@ __arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) __builtin_mve_vst4qv4sf (__addr, __rv.__o); } +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndxq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndxq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndpq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndpq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndnq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndnq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndmq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndmq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndaq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndaq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev64q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f32 (float32x4_t __a) +{ + return __builtin_mve_vrev64q_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f16 (float16x8_t __a) +{ + return __builtin_mve_vnegq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f32 (float32x4_t __a) +{ + return __builtin_mve_vnegq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f16 (float16_t __a) +{ + return __builtin_mve_vdupq_n_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f32 (float32_t __a) +{ + return __builtin_mve_vdupq_n_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f16 (float16x8_t __a) +{ + return __builtin_mve_vabsq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f32 (float32x4_t __a) +{ + return __builtin_mve_vabsq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev32q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvttq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtbq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_s16 (int16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_s32 (int32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_u16 (uint16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_u32 (uint32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv4sf (__a); +} + #endif enum { @@ -368,6 +584,83 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) +#define vrndxq(p0) __arm_vrndxq(p0) +#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndq(p0) __arm_vrndq(p0) +#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndpq(p0) __arm_vrndpq(p0) +#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndnq(p0) __arm_vrndnq(p0) +#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndmq(p0) __arm_vrndmq(p0) +#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndaq(p0) __arm_vrndaq(p0) +#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev64q(p0) __arm_vrev64q(p0) +#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vnegq(p0) __arm_vnegq(p0) +#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vabsq(p0) __arm_vabsq(p0) +#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev32q(p0) __arm_vrev32q(p0) +#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) +#define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) +#define __arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtq(p0) __arm_vcvtq(p0) +#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + #else /* MVE Interger. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index c7f3546c9cb0ec3ae794e181e533a1cbed38121c..65dc58c9328525891a0aa0bb97a412ebc8257c18 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -19,3 +19,18 @@ <http://www.gnu.org/licenses/>. */ VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf) +VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf) +VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) +VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) +VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) +VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 9b3bb6129a99c4f3c952e7a72d0874dcba12f30d..e5f7e1d61da84e6cb608dd3d37dee6b12c76eea3 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -21,8 +21,18 @@ (V2DI "u64")]) (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) +(define_mode_iterator MVE_0 [V8HF V4SF]) -(define_c_enum "unspec" [VST4Q]) +(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F + VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F + VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S + VCVTQ_TO_F_U]) + +(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") + (V8HF "V8HI") (V4SF "V4SI")]) + +(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")]) +(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_insn "*mve_mov<mode>" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -120,3 +130,198 @@ return ""; } [(set_attr "length" "16")]) + +;; +;; [vrndxq_f]) +;; +(define_insn "mve_vrndxq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDXQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintx.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndq_f]) +;; +(define_insn "mve_vrndq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintz.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndpq_f]) +;; +(define_insn "mve_vrndpq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDPQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintp.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndnq_f]) +;; +(define_insn "mve_vrndnq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDNQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintn.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndmq_f]) +;; +(define_insn "mve_vrndmq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDMQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintm.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndaq_f]) +;; +(define_insn "mve_vrndaq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDAQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrinta.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev64q_f]) +;; +(define_insn "mve_vrev64q_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VREV64Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrev64.%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vnegq_f]) +;; +(define_insn "mve_vnegq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VNEGQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vneg.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vdupq_n_f]) +;; +(define_insn "mve_vdupq_n_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")] + VDUPQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vdup.%#<V_sz_elem> %q0, %1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vabsq_f]) +;; +(define_insn "mve_vabsq_f<mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VABSQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vabs.f%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev32q_f]) +;; +(define_insn "mve_vrev32q_fv8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")] + VREV32Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrev32.16 %q0, %q1" + [(set_attr "type" "mve_move") +]) +;; +;; [vcvttq_f32_f16]) +;; +(define_insn "mve_vcvttq_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] + VCVTTQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtt.f32.f16 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtbq_f32_f16]) +;; +(define_insn "mve_vcvtbq_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] + VCVTBQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtb.f32.f16 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtq_to_f_s, vcvtq_to_f_u]) +;; +(define_insn "mve_vcvtq_to_f_<supf><mode>" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] + VCVTQ_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem> %q0, %q1" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..f49807cb863cb0bf7718e742692756d3a6a8311e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vabsq_f16 (a); +} + +/* { dg-final { scan-assembler "vabs.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..ab44b314c3895a77d4c6a3591386a7ad300c95c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vabsq_f32 (a); +} + +/* { dg-final { scan-assembler "vabs.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..bc57f261f2ca3d6b66e05553dc8069e88d9b8ba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a) +{ + return vcvtbq_f32_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..9a7d9c2cf7eca3d1501cbf945625ab807b067558 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (int16x8_t a) +{ + return vcvtq_f16_s16 (a); +} + +/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..6aae96862c4a389b25dba3cd194c73ebc1e7ee96 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (uint16x8_t a) +{ + return vcvtq_f16_u16 (a); +} + +/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..b563fe972bd08173ff3c2cadce975523d434d127 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (int32x4_t a) +{ + return vcvtq_f32_s32 (a); +} + +/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..f5354a4a02faeab5d33798a3821e00838702eaa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t a) +{ + return vcvtq_f32_u32 (a); +} + +/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..2c0f4fda6be551651cb1fa631eb4a80dc8a75a3b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a) +{ + return vcvttq_f32_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..616c24fd3aaf92603a207051f62af87a3b968769 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t a) +{ + return vdupq_n_f16 (a); +} + +/* { dg-final { scan-assembler "vdup.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..570dfde905f2858f6280474d99d7c01e28a320cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t a) +{ + return vdupq_n_f32 (a); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..89d0162c274924199f5ef487232aaf0d057a1315 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vnegq_f16 (a); +} + +/* { dg-final { scan-assembler "vneg.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..8cbdd16342da17151afafa80e493a217ec4c3c2a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vnegq_f32 (a); +} + +/* { dg-final { scan-assembler "vneg.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..86bf47dea54965aee76d7066188367c8bd1c109f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrev32q_f16 (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..d7f75fd9d3dbb4c0cc2cad4c108d900c59b8b253 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrev64q_f16 (a); +} + +/* { dg-final { scan-assembler "vrev64.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..131ec461b0ed0bd52cd474d4a9303a0717b95f36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrev64q_f32 (a); +} + +/* { dg-final { scan-assembler "vrev64.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..d647d31ac705bce5265ecf8dd4230736d8306da4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndaq_f16 (a); +} + +/* { dg-final { scan-assembler "vrinta.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..4d5ba502bc57269a9395c3287ad7902fd570a788 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndaq_f32 (a); +} + +/* { dg-final { scan-assembler "vrinta.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..996b0b27c159114283fed2b5f62861ea93b38b15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndmq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintm.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..fae0a5ca2f15305d23d39b189ab0bb1a640618a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndmq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintm.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..cc00b6eb6131f726055a00bd3175fa1a637210f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndnq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintn.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..150e9d38342b68bc48a9d3d0c62c6d721e8876a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndnq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintn.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..d75ea35c02cef41133d8750a408d0a072c82fa1b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndpq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..45de7fb5c591f4e481a575eb231d3e2758bb5dfa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndpq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..b3a96540508fbe57999ea8d3a37b477ebb3b5193 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintz.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..c8a723ae4d7f79ff4c798962d14d80375da8faa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintz.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..aa364f0671fea913dfb421aab5731a2afb87d99b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndxq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintx.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..99a758110c7558fac5cbea522c33a8267a49aab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndxq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintx.f32" } } */