From patchwork Fri Dec 6 17:38:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 298143 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5560D2C00A8 for ; Sat, 7 Dec 2013 04:38:22 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=ls7uTNp42N30b+WhI5 YHplAQGO1NopJhAXmVp4eEwmUggoYRZds/VV2cPOpmQBopjoubwRCSeFP0YdI4cf qDnfq5Kg6eN0gQLe4eaZAZ1t4mzjKGq0S5xcdaVLKS1tnAAlVamU4fL+0QP2Mq9V JVO2Jg1mgpOnMYqTm3+FSAiYI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=bOf3cOBM2Vxo7VaRT8Ajui6V zT4=; b=Z5sgFqZnmqz7RNa4X4ElJa7X/7TLv1q9d/ZbwrxF5mTWsvn4Mwl4RbY0 OCB+01Ma6DxQxu+M+nLaa/KqkE2893m1ozuaQK/yU7NWKtrQ0Ji2I9Op6DCac7F7 h57tIKc/5rb2Rlnbt3tJ9aMToRDg0RR46tY719R7c5Hlkiy3PiI= Received: (qmail 8316 invoked by alias); 6 Dec 2013 17:38:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 8304 invoked by uid 89); 6 Dec 2013 17:38:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f178.google.com Received: from Unknown (HELO mail-ob0-f178.google.com) (209.85.214.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 06 Dec 2013 17:38:14 +0000 Received: by mail-ob0-f178.google.com with SMTP id uz6so1105944obc.9 for ; Fri, 06 Dec 2013 09:38:06 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.182.87.42 with SMTP id u10mr3354972obz.22.1386351486674; Fri, 06 Dec 2013 09:38:06 -0800 (PST) Received: by 10.76.105.174 with HTTP; Fri, 6 Dec 2013 09:38:06 -0800 (PST) In-Reply-To: References: <20131205182254.GA17941@intel.com> <52A0E9E0.5070508@gmail.com> Date: Fri, 6 Dec 2013 09:38:06 -0800 Message-ID: Subject: Re: [PATCH] Add -mtune=ia support From: "H.J. Lu" To: Uros Bizjak Cc: Richard Biener , Patrick Marlier , GCC Patches X-IsSubscribed: yes On Fri, Dec 6, 2013 at 2:44 AM, Uros Bizjak wrote: > On Fri, Dec 6, 2013 at 10:38 AM, Richard Biener > wrote: >> On Thu, Dec 5, 2013 at 10:05 PM, H.J. Lu wrote: >>> On Thu, Dec 5, 2013 at 1:02 PM, Patrick Marlier >>> wrote: >>>> Hi, >>>> >>>> >>>> On 12/05/2013 07:22 PM, H.J. Lu wrote: >>>>> >>>>> We'd like to add a new -mtune=ia option for x86 to optimize for both >>>>> Haswell and Silvermont. Currently, -mtune=ia is aliased to -mtune=slm. >>>>> We will improve it further for Haswell and Silvermont. Later, we will >>>>> update it to future Intel processors. >>>> >>>> >>>> At first, 'ia' means to me Itanium, ie IA-64. I would personally prefer >>>> another name but maybe I am the only one to think that. >>>> >>> >>> "ia" stands for Intel Architecture. It is the natural name for >>> this option. >> >> I think "ia" and the natural "aa" are too obfuscated. Why didn't you >> chose simply "intel" here? (will the next patch add -mtune=a as >> that's natural for "AMD"?) > > -mtune=intel indeed sounds better. > This is the patch I checked in. Thanks. diff --git a/gcc/config.gcc b/gcc/config.gcc index dd180a0..dc76c82 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1398,7 +1398,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'` need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xintel|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1407,7 +1407,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic ia atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic intel atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1519,7 +1519,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*) tmake_file="$tmake_file i386/t-sol2-64" need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xintel|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1528,7 +1528,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic ia atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic intel atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1604,7 +1604,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) if test x$enable_targets = xall; then tm_defines="${tm_defines} TARGET_BI_ARCH=1" case X"${with_cpu}" in - Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xintel|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1613,7 +1613,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic ia atom slm core2 corei7 Xcorei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic intel atom slm core2 corei7 Xcorei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -3664,7 +3664,7 @@ case "${target}" in esac # OK ;; - "" | x86-64 | generic | ia | native \ + "" | x86-64 | generic | intel | native \ | k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \ | opteron-sse3 | athlon-fx | bdver4 | bdver3 | bdver2 \ | bdver1 | btver2 | btver1 | amdfam10 | barcelona \ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 382f8fb..26fff53 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2434,7 +2434,7 @@ static const char *const cpu_names[TARGET_CPU_DEFAULT_max] = "core-avx2", "atom", "slm", - "ia", + "intel", "geode", "k6", "k6-2", @@ -3143,7 +3143,7 @@ ix86_option_override_internal (bool main_args_p, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR}, - {"ia", PROCESSOR_SLM, CPU_SLM, + {"intel", PROCESSOR_SLM, CPU_SLM, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR}, {"geode", PROCESSOR_GEODE, CPU_GEODE, @@ -3632,8 +3632,8 @@ ix86_option_override_internal (bool main_args_p, if (!strcmp (opts->x_ix86_arch_string, "generic")) error ("generic CPU can be used only for %stune=%s %s", prefix, suffix, sw); - else if (!strcmp (ix86_arch_string, "ia")) - error ("ia CPU can be used only for %stune=%s %s", + else if (!strcmp (ix86_arch_string, "intel")) + error ("intel CPU can be used only for %stune=%s %s", prefix, suffix, sw); else if (!strncmp (opts->x_ix86_arch_string, "generic", 7) || i == pta_size) error ("bad value (%s) for %sarch=%s %s", diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index db81aea..7efd1e0 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -626,7 +626,7 @@ enum target_cpu_default TARGET_CPU_DEFAULT_haswell, TARGET_CPU_DEFAULT_atom, TARGET_CPU_DEFAULT_slm, - TARGET_CPU_DEFAULT_ia, + TARGET_CPU_DEFAULT_intel, TARGET_CPU_DEFAULT_geode, TARGET_CPU_DEFAULT_k6, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cfb9b38..76149a3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14778,11 +14778,11 @@ generic instruction set applicable to all processors. In contrast, @option{-mtune} indicates the processor (or, in this case, collection of processors) for which the code is optimized. -@item ia +@item intel Produce code optimized for the most current Intel processors, which are Haswell and Silvermont for this version of GCC. If you know the CPU on which your code will run, then you should use the corresponding -@option{-mtune} or @option{-march} option instead of @option{-mtune=ia}. +@option{-mtune} or @option{-march} option instead of @option{-mtune=intel}. But, if you want your application performs better on both Haswell and Silvermont, then you should use this option.