From patchwork Sun Mar 24 12:13:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongtao Liu X-Patchwork-Id: 1063113 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-498347-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="s4ycwHks"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="u8i0ImxU"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44RxBX1rHpz9sRk for ; Sun, 24 Mar 2019 23:13:33 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; q=dns; s=default; b=iftqXeo0Snjs9Bp9qf9lozbSwIZ++pFW2K6BWJW69BH /2/8Z8NZAUxaLgpLaA75CotqialsOAIgKyNab7nsFyviCwKjmaPK8m9VKRWWVjyC HdnxzZIcNw5XZMi5XGjtiZEYZI/Aj/FhvRZy4Re0oogMzJOGyhfgRgd+ZUiUVgME = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:cc:content-type; s=default; bh=RZ2v+uLX4ZL9WalcvcgmCDZVSO4=; b=s4ycwHksOOT11slK8 wXknW4tcSX2+J56k0ZioUYs3s0LsG4j6vI98Uj6Ly4dYlCeRkfT1EuJRpVN266L9 qkgE0+EJvEY+eiRWkGH2fe84CgknFZrfAt1T64v3YSTFWcg0hBW9gcpAWf/eBl7v Cbgq/MHU9PEX8UwCdoEVYLRYPs= Received: (qmail 127641 invoked by alias); 24 Mar 2019 12:13:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 127633 invoked by uid 89); 24 Mar 2019 12:13:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-9.2 required=5.0 tests=BAYES_40, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=_mask, UD:sse-13.c, sse-23.c, sk:hongtao X-HELO: mail-ot1-f52.google.com Received: from mail-ot1-f52.google.com (HELO mail-ot1-f52.google.com) (209.85.210.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 24 Mar 2019 12:13:19 +0000 Received: by mail-ot1-f52.google.com with SMTP id c16so5682773otn.4 for ; Sun, 24 Mar 2019 05:13:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc; bh=q6h0wRlMc6RQEEtbTKldfK54TpN7gqmLL1B6xnatA8A=; b=u8i0ImxUXb67rRtdEg/p+zkTYmmx7et4bsbasAucQAyPWcBVUxvOqI7Vx44O2DHth0 qN0Mvj9qvmiho2HUfdEdrojgFSHsppwBjFj7t8++xj/UgGOZrRlwumyzTqu76VXlzEBz Qc6jc53Ozq4/VWC2ic7ZrtTuSh1GMHMj6i/7/Aq8wv8mwlgvxuVOXxnPGPyDkjHOYFUP 5CxHz0g5U+xi+0eKKgAgHhCS9AyG636VgDN0hWTeTO08aOLfTXwAZs2r/LqLWqphprgA QNkV1MPTVV4MXZ3nmcveYmAvyRZZFk3Br/JBuB4/9RBFQ7gceMAycU2AV8kCSMU47tn2 5bbg== MIME-Version: 1.0 From: Hongtao Liu Date: Sun, 24 Mar 2019 20:13:05 +0800 Message-ID: Subject: [PATCH] Add missing avx512dqintrin.h _mm_mask_fpclass_s[sd]_mask (PR target/897803) To: Uros Bizjak , jakub@redhat.com, "H. J. Lu" Cc: gcc-patches@gcc.gnu.org X-IsSubscribed: yes Hi: The following patch adds forgotten avx512f fpclass instrinsics for masked scalar operations. Bootstrapped/regtested on x86_64-linux and i686-linux (on skylake-avx512), ok for trunk? #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C) #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C) #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D) Index: ChangeLog =================================================================== --- ChangeLog (revision 269894) +++ ChangeLog (working copy) @@ -1,3 +1,16 @@ +2019-03-24 Hongtao Liu + + PR target/89803 + * config/i386/avx512dqintrin.h + (_mm_mask_fpclass_ss_mask,_mm_mask_fpclass_sd_mask): + New intrinsics. + * config/i386/i386-builtin.def + (__builtin_ia32_fpclassss_mask, _builtin_ia32_fpclasssd_mask): + New builtins. + * config/i386/sse.md + (define_insn "avx512dq_vmfpclass): + Modified with mask. + 2019-03-23 Segher Boessenkool * config/rs6000/xmmintrin.h (_mm_movemask_pi8): Implement for 32-bit Index: config/i386/avx512dqintrin.h =================================================================== --- config/i386/avx512dqintrin.h (revision 269894) +++ config/i386/avx512dqintrin.h (working copy) @@ -1372,6 +1372,20 @@ return (__mmask8) __builtin_ia32_fpclasssd ((__v2df) __A, __imm); } +extern __inline __mmask8 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_fpclass_ss_mask (__mmask8 __U, __m128 __A, const int __imm) +{ + return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, __U); +} + +extern __inline __mmask8 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const int __imm) +{ + return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, __U); +} + extern __inline __m512i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm512_cvtt_roundpd_epi64 (__m512d __A, const int __R) @@ -2623,6 +2637,12 @@ #define _mm_fpclass_sd_mask(X, C) \ ((__mmask8) __builtin_ia32_fpclasssd ((__v2df) (__m128d) (X), (int) (C))) \ +#define _mm_mask_fpclass_ss_mask(X, C, U) \ + ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), (int) (C)), (__mmask8) (U)) + +#define _mm_mask_fpclass_sd_mask(X, C, U) \ + ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), (int) (C)), (__mmask8) (U)) + #define _mm512_mask_fpclass_pd_mask(u, X, C) \ ((__mmask8) __builtin_ia32_fpclasspd512_mask ((__v8df) (__m512d) (X), \ (int) (C), (__mmask8)(u))) Index: config/i386/i386-builtin.def =================================================================== --- config/i386/i386-builtin.def (revision 269894) +++ config/i386/i386-builtin.def (working copy) @@ -2082,9 +2082,11 @@ BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT) +BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df_mask, "__builtin_ia32_fpclasssd_mask", IX86_BUILTIN_FPCLASSSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT) +BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf_mask, "__builtin_ia32_fpclassss_mask", IX86_BUILTIN_FPCLASSSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) UHI_FTYPE_V16QI) BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) USI_FTYPE_V32QI) BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) UQI_FTYPE_V8HI) Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 269894) +++ config/i386/sse.md (working copy) @@ -21111,7 +21111,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512dq_vmfpclass" +(define_insn "avx512dq_vmfpclass" [(set (match_operand: 0 "register_operand" "=k") (and: (unspec: @@ -21120,7 +21120,7 @@ UNSPEC_FPCLASS) (const_int 1)))] "TARGET_AVX512DQ" - "vfpclass\t{%2, %1, %0|%0, %1, %2}"; + "vfpclass\t{%2, %1, %0|%0, %1, %2}"; [(set_attr "type" "sse") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") Index: testsuite/ChangeLog =================================================================== --- testsuite/ChangeLog (revision 269894) +++ testsuite/ChangeLog (working copy) @@ -1,3 +1,19 @@ +2019-03-24 Hongtao Liu + + PR target/89803 + * gcc.target/i386/avx-1.c (__builtin_ia32_fpclassss_mask, + __builtin_ia32_fpclasssd_mask): Define. + * gcc.target/i386/sse-13.c (__builtin_ia32_fpclassss_mask, + __builtin_ia32_fpclasssd_mask): Likewise. + * gcc.target/i386/sse-23.c (__builtin_ia32_fpclassss_mask) + (__builtin_ia32_fpclasssd_mask): Likewise. + * gcc.target/i386/avx512dq-vfpclassss-2.c: New. + * gcc.target/i386/avx512dq-vfpclasssd-2.c: Likewise. + * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test): + Add test for _mm_mask_fpclass_ss_mask. + * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test): + Add test for _mm_mask_fpclass_sd_mask. + 2019-03-22 Vladimir Makarov PR rtl-optimization/89676 Index: testsuite/gcc.target/i386/avx-1.c =================================================================== --- testsuite/gcc.target/i386/avx-1.c (revision 269894) +++ testsuite/gcc.target/i386/avx-1.c (working copy) @@ -446,6 +446,8 @@ #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E) #define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1) #define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1) +#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U) +#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U) #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C) #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C) #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D) Index: testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c =================================================================== --- testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c (revision 269894) +++ testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512dq -O2" } */ /* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -11,4 +12,5 @@ avx512dq_test (void) { m8 = _mm_fpclass_sd_mask (x128, 13); + m8 = _mm_mask_fpclass_sd_mask (m8, x128, 13); } Index: testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c =================================================================== --- testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c (nonexistent) +++ testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c (working copy) @@ -0,0 +1,75 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512dq" } */ +/* { dg-require-effective-target avx512dq } */ + +#define AVX512DQ +#include "avx512f-helper.h" + +#include +#include +#include +#define SIZE (128 / 64) +#include "avx512f-mask-type.h" + +#ifndef __FPCLASSSD__ +#define __FPCLASSSD__ +int check_fp_class_dp (double src, int imm) +{ + int qNaN_res = isnan (src); + int sNaN_res = isnan (src); + int Pzero_res = (src == 0.0); + int Nzero_res = (src == -0.0); + int PInf_res = (isinf (src) == 1); + int NInf_res = (isinf (src) == -1); + int Denorm_res = (fpclassify (src) == FP_SUBNORMAL); + int FinNeg_res = __builtin_finite (src) && (src < 0); + + int result = (((imm & 1) && qNaN_res) + || (((imm >> 1) & 1) && Pzero_res) + || (((imm >> 2) & 1) && Nzero_res) + || (((imm >> 3) & 1) && PInf_res) + || (((imm >> 4) & 1) && NInf_res) + || (((imm >> 5) & 1) && Denorm_res) + || (((imm >> 6) & 1) && FinNeg_res) + || (((imm >> 7) & 1) && sNaN_res)); + return result; +} +#endif + +__mmask8 +CALC (double *s1, int imm) +{ + int i; + __mmask8 res = 0; + + if (check_fp_class_dp(s1[0], imm)) + res = res | 1; + + return res; +} + +void +TEST (void) +{ + int i; + union128d src; + __mmask8 res1, res2, res_ref = 0; + __mmask8 mask = MASK_VALUE; + + src.a[0] = 1.0 / 0.0; + for (i = 1; i < SIZE; i++) + { + src.a[i] = -24.43 + 0.6 * i; + } + + res1 = _mm_fpclass_sd_mask (src.x, 0xFF); + res2 = _mm_mask_fpclass_sd_mask (mask, src.x, 0xFF); + + res_ref = CALC (src.a, 0xFF); + + if (res_ref != res1) + abort (); + + if ((res_ref & mask) != res2) + abort (); +} Index: testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c =================================================================== --- testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c (revision 269894) +++ testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c (working copy) @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512dq -O2" } */ /* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -11,4 +12,5 @@ avx512dq_test (void) { m8 = _mm_fpclass_ss_mask (x128, 13); + m8 = _mm_mask_fpclass_ss_mask (m8, x128, 13); } Index: testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c =================================================================== --- testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c (nonexistent) +++ testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c (working copy) @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512dq" } */ +/* { dg-require-effective-target avx512dq } */ + +#define AVX512DQ +#include "avx512f-helper.h" + +#include +#include +#include +#include "avx512f-mask-type.h" +#define SIZE (128 / 32) + +#ifndef __FPCLASSSS__ +#define __FPCLASSSS__ +int check_fp_class_sp (float src, int imm) +{ + int qNaN_res = isnan (src); + int sNaN_res = isnan (src); + int Pzero_res = (src == 0.0); + int Nzero_res = (src == -0.0); + int PInf_res = (isinf (src) == 1); + int NInf_res = (isinf (src) == -1); + int Denorm_res = (fpclassify (src) == FP_SUBNORMAL); + int FinNeg_res = __builtin_finite (src) && (src < 0); + + int result = (((imm & 1) && qNaN_res) + || (((imm >> 1) & 1) && Pzero_res) + || (((imm >> 2) & 1) && Nzero_res) + || (((imm >> 3) & 1) && PInf_res) + || (((imm >> 4) & 1) && NInf_res) + || (((imm >> 5) & 1) && Denorm_res) + || (((imm >> 6) & 1) && FinNeg_res) + || (((imm >> 7) & 1) && sNaN_res)); + return result; +} +#endif + +__mmask8 +CALC (float *s1, int imm) +{ + int i; + __mmask8 res = 0; + + if (check_fp_class_sp(s1[0], imm)) + res = res | 1; + + return res; +} + +void +TEST (void) +{ + int i; + union128 src; + __mmask8 res1, res2, res_ref = 0; + __mmask8 mask = MASK_VALUE; + + src.a[0] = 1.0 / 0.0; + for (i = 1; i < SIZE; i++) + { + src.a[i] = -24.43 + 0.6 * i; + } + + res1 = _mm_fpclass_ss_mask (src.x, 0xFF); + res2 = _mm_mask_fpclass_ss_mask (mask, src.x, 0xFF); + + + res_ref = CALC (src.a, 0xFF); + + if (res_ref != res1) + abort (); + + if ((mask & res_ref) != res2) + abort (); +} Index: testsuite/gcc.target/i386/sse-13.c =================================================================== --- testsuite/gcc.target/i386/sse-13.c (revision 269894) +++ testsuite/gcc.target/i386/sse-13.c (working copy) @@ -463,6 +463,8 @@ #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E) #define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1) #define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1) +#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U) +#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U) #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C) #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C) #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D) Index: testsuite/gcc.target/i386/sse-23.c =================================================================== --- testsuite/gcc.target/i386/sse-23.c (revision 269894) +++ testsuite/gcc.target/i386/sse-23.c (working copy) @@ -462,6 +462,8 @@ #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E) #define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1) #define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1) +#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U) +#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U)